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authorJack Koenig2021-09-11 00:29:10 -0700
committerGitHub2021-09-11 00:29:10 -0700
commitbeb5bc9850fd69adff36f38fb00a1f68bb1918fe (patch)
tree7288c60abd0a4507df57acddea80232cdae9ca95 /src/test/scala/firrtlTests/transforms
parentc7917c88f8e8aaa93255a731c75f3e0e6901e2fb (diff)
Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
Diffstat (limited to 'src/test/scala/firrtlTests/transforms')
-rw-r--r--src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala47
1 files changed, 45 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
index 81b5fd5d..45be4cb3 100644
--- a/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlackBoxSourceHelperSpec.scala
@@ -2,16 +2,37 @@
package firrtlTests.transforms
-import firrtl.annotations.{CircuitName, ModuleName}
+import firrtl.annotations._
import firrtl.transforms._
-import firrtl.{Transform, VerilogEmitter}
+import firrtl._
import firrtl.FileUtils
import firrtl.testutils.LowTransformSpec
+import firrtl.stage._
+import firrtl.options.Dependency
+import java.io.File
+import firrtl.util.BackendCompilationUtilities.createTestDirectory
+import _root_.logger._
+
+class ChangeBlackBoxTargetDir extends Transform with DependencyAPIMigration {
+ override def prerequisites =
+ Dependency[firrtl.passes.memlib.ReplSeqMem] +: Forms.LowFormOptimized
+ override def optionalPrerequisiteOf = Forms.BackendEmitters
+ override def invalidates(a: Transform): Boolean = false
+
+ def execute(state: CircuitState): CircuitState = {
+ val annosx = state.annotations.map {
+ case BlackBoxTargetDirAnno(dir) => BlackBoxTargetDirAnno(s"$dir/subdir")
+ case other => other
+ }
+ state.copy(annotations = annosx)
+ }
+}
class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
def transform: Transform = new BlackBoxSourceHelper
private val moduleName = ModuleName("Top", CircuitName("Top"))
+ private val bbTarget = CircuitTarget("Top").module("AdderExtModule")
private val input = """
|circuit Top :
|
@@ -150,4 +171,26 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
)
}
+ "BlackBoxSourceHelper" should "not run until late" in {
+ val name = "BlackBoxSourceHelper_late"
+
+ val dir = createTestDirectory(name)
+ val subdir = new File(dir, "subdir")
+
+ val filename = "BFFAdd.v"
+
+ val annos = List(
+ FirrtlSourceAnnotation(input),
+ RunFirrtlTransformAnnotation(new ChangeBlackBoxTargetDir),
+ BlackBoxTargetDirAnno(dir.toString),
+ BlackBoxInlineAnno(bbTarget, filename, "<contentx>"),
+ EmitCircuitAnnotation(classOf[VerilogEmitter]),
+ LogLevelAnnotation(LogLevel.Debug)
+ )
+
+ (new FirrtlPhase).transform(annos)
+
+ new File(subdir, filename) should exist
+ new File(dir, filename) shouldNot exist
+ }
}