diff options
| author | Schuyler Eldridge | 2020-08-01 13:01:44 -0400 |
|---|---|---|
| committer | GitHub | 2020-08-01 17:01:44 +0000 |
| commit | 687f3ddbbcd9217542a4bc0e2c256559d2c67a5b (patch) | |
| tree | 056f4ef5c9f3aabf370599264a47f8831f8d8722 /src/test/scala/firrtlTests/transforms | |
| parent | a82958714c096eefebde16e0491b978135c1757e (diff) | |
Error on ExtModules w/ same defname, diff. ports (#1734)
* Use signed output in LargeParamExecutionTest
Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/test/scala/firrtlTests/transforms')
| -rw-r--r-- | src/test/scala/firrtlTests/transforms/DedupTests.scala | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala index 5776db31..8ab3026c 100644 --- a/src/test/scala/firrtlTests/transforms/DedupTests.scala +++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala @@ -193,13 +193,13 @@ class DedupModuleTests extends HighTransformSpec { | module A_ : @[xx 1:1] | output y: UInt<1> @[xx 1:1] | inst c of C - | y <= c.v + | y <= c.u | extmodule B : @[aa 3:3] | output u : UInt<1> @[aa 4:4] | defname = BB | parameter N = 0 | extmodule C : @[bb 5:5] - | output v : UInt<1> @[bb 6:6] + | output u : UInt<1> @[bb 6:6] | defname = BB | parameter N = 0 """.stripMargin @@ -238,13 +238,13 @@ class DedupModuleTests extends HighTransformSpec { | module A_ : @[xx 1:1] | output y: UInt<1> @[xx 1:1] | inst c of C - | y <= c.v + | y <= c.u | extmodule B : @[aa 3:3] | output u : UInt<1> @[aa 4:4] | defname = ${defnames._1} | parameter N = ${params._1} | extmodule C : @[bb 5:5] - | output v : UInt<1> @[bb 6:6] + | output u : UInt<1> @[bb 6:6] | defname = ${defnames._2} | parameter N = ${params._2} """.stripMargin @@ -875,4 +875,3 @@ class DedupModuleTests extends HighTransformSpec { csDeduped.annotations.toSeq should contain (expectedAnnB) } } - |