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authorSchuyler Eldridge2020-01-09 13:02:36 -0500
committermergify[bot]2020-01-09 18:02:36 +0000
commit2dc005d500ffcccef5def5938dc7ead7c68644b3 (patch)
treeb64a952e0bd9bb5fe1a5e7c04e7e373f197f46b2 /src/test/scala/firrtlTests/transforms
parenta4f2eda0ca312f80f43f89a764622aa744f9f84b (diff)
Dedup PassTests, add NoCircuitDedupAnnotations (#1302)
Change PassTests to include Dedup when running transforms. This makes PassTests behave more like an actual compiler. Fixes bugs in Inline, Flatten, and Grouping tests where the tests would only work without deduplication. This adds NoCircuiDedupAnnotations to prevent deduplication for the offending tests. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/test/scala/firrtlTests/transforms')
-rw-r--r--src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala23
1 files changed, 13 insertions, 10 deletions
diff --git a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
index f731073b..b4ecf058 100644
--- a/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/GroupComponentsSpec.scala
@@ -2,7 +2,7 @@ package firrtlTests
package transforms
import firrtl.annotations.{CircuitName, ComponentName, ModuleName}
-import firrtl.transforms.{GroupAnnotation, GroupComponents}
+import firrtl.transforms.{GroupAnnotation, GroupComponents, NoCircuitDedupAnnotation}
import firrtl._
import firrtl.ir._
@@ -112,9 +112,10 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
- val groups = Seq(
+ val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a")/*, topComp("asum")*/), "A", "cA", Some("_OUT"), Some("_IN")),
- GroupAnnotation(Seq(topComp("c1b"), topComp("c2b")/*, topComp("bsum")*/), "B", "cB", Some("_OUT"), Some("_IN"))
+ GroupAnnotation(Seq(topComp("c1b"), topComp("c2b")/*, topComp("bsum")*/), "B", "cB", Some("_OUT"), Some("_IN")),
+ NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
@@ -152,7 +153,7 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
- execute(input, check, groups)
+ execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with their nodes" in {
val input =
@@ -179,9 +180,10 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
- val groups = Seq(
+ val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a"), topComp("asum")), "A", "cA", Some("_OUT"), Some("_IN")),
- GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN"))
+ GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN")),
+ NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
@@ -215,7 +217,7 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt<8>
| out <= UInt(2)
""".stripMargin
- execute(input, check, groups)
+ execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with one not grouped" in {
@@ -249,9 +251,10 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt
| out <= in
""".stripMargin
- val groups = Seq(
+ val annotations = Seq(
GroupAnnotation(Seq(topComp("c1a"), topComp("c2a"), topComp("asum")), "A", "cA", Some("_OUT"), Some("_IN")),
- GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN"))
+ GroupAnnotation(Seq(topComp("c1b"), topComp("c2b"), topComp("bsum")), "B", "cB", Some("_OUT"), Some("_IN")),
+ NoCircuitDedupAnnotation
)
val check =
s"""circuit Top :
@@ -291,7 +294,7 @@ class GroupComponentsSpec extends MiddleTransformSpec {
| output out: UInt<10>
| out <= in
""".stripMargin
- execute(input, check, groups)
+ execute(input, check, annotations)
}
"The two sets of instances" should "be grouped with a connection between them" in {