All of src/ formatted with scalafmt

6 files changed, 179 insertions, 157 deletions

diff --git a/src/test/scala/firrtlTests/annotationTests/CleanupNamedTargetsSpec.scala b/src/test/scala/firrtlTests/annotationTests/CleanupNamedTargetsSpec.scala
index 58cb3d11..67408bb7 100644
--- a/src/test/scala/firrtlTests/annotationTests/CleanupNamedTargetsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/CleanupNamedTargetsSpec.scala
@@ -11,7 +11,8 @@ import firrtl.annotations.{
   MultiTargetAnnotation,
   ReferenceTarget,
   SingleTargetAnnotation,
-  Target}
+  Target
+}
 import firrtl.annotations.transforms.CleanupNamedTargets
 
 import org.scalatest.flatspec.AnyFlatSpec
@@ -56,7 +57,7 @@ class CleanupNamedTargetsSpec extends AnyFlatSpec with Matchers {
 
   }
 
-  behavior of "CleanupNamedTargets"
+  behavior.of("CleanupNamedTargets")
 
   it should "convert a SingleTargetAnnotation[ReferenceTarget] of an instance to an InstanceTarget" in new F {
     val annotations: AnnotationSeq = Seq(SingleReferenceAnnotation(barTarget))
@@ -71,10 +72,10 @@ class CleanupNamedTargetsSpec extends AnyFlatSpec with Matchers {
 
     val renames = transform.transform(circuitState(annotations)).renames.get
 
-    renames.get(barTarget) should be (Some(Seq(foo.instOf("bar", "Bar"))))
+    renames.get(barTarget) should be(Some(Seq(foo.instOf("bar", "Bar"))))
 
     info("and not touch a true ReferenceAnnotation")
-    renames.get(bazTarget) should be (None)
+    renames.get(bazTarget) should be(None)
 
   }
 
diff --git a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
index 73f36cf0..bb833f0b 100644
--- a/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
@@ -6,7 +6,7 @@ import firrtl._
 import firrtl.annotations._
 import firrtl.annotations.analysis.DuplicationHelper
 import firrtl.annotations.transforms.{NoSuchTargetException}
-import firrtl.transforms.{DontTouchAnnotation, DedupedResult}
+import firrtl.transforms.{DedupedResult, DontTouchAnnotation}
 import firrtl.testutils.{FirrtlMatchers, FirrtlPropSpec}
 
 object EliminateTargetPathsSpec {
@@ -15,7 +15,7 @@ object EliminateTargetPathsSpec {
     override def duplicate(n: Target): Annotation = DummyAnnotation(n)
   }
   class DummyTransform() extends Transform with ResolvedAnnotationPaths {
-    override def inputForm: CircuitForm = LowForm
+    override def inputForm:  CircuitForm = LowForm
     override def outputForm: CircuitForm = LowForm
 
     override val annotationClasses: Traversable[Class[_]] = Seq(classOf[DummyAnnotation])
@@ -72,40 +72,47 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
   property("Hierarchical tokens should be expanded properly") {
     val dupMap = DuplicationHelper(inputState.circuit.modules.map(_.name).toSet)
 
-
     // Only a few instance references
     dupMap.expandHierarchy(Top_m1_l1_a)
     dupMap.expandHierarchy(Top_m2_l1_a)
     dupMap.expandHierarchy(Middle_l1_a)
 
-    dupMap.makePathless(Top_m1_l1_a).foreach {Set(TopCircuit.module("Leaf___Top_m1_l1").ref("a")) should contain (_)}
-    dupMap.makePathless(Top_m2_l1_a).foreach {Set(TopCircuit.module("Leaf___Top_m2_l1").ref("a")) should contain (_)}
-    dupMap.makePathless(Top_m1_l2_a).foreach {Set(Leaf_a) should contain (_)}
-    dupMap.makePathless(Top_m2_l2_a).foreach {Set(Leaf_a) should contain (_)}
-    dupMap.makePathless(Middle_l1_a).foreach {Set(
-      TopCircuit.module("Leaf___Top_m1_l1").ref("a"),
-      TopCircuit.module("Leaf___Top_m2_l1").ref("a"),
-      TopCircuit.module("Leaf___Middle_l1").ref("a")
-    ) should contain (_) }
-    dupMap.makePathless(Middle_l2_a).foreach {Set(Leaf_a) should contain (_)}
-    dupMap.makePathless(Leaf_a).foreach {Set(
-      TopCircuit.module("Leaf___Top_m1_l1").ref("a"),
-      TopCircuit.module("Leaf___Top_m2_l1").ref("a"),
-      TopCircuit.module("Leaf___Middle_l1").ref("a"),
-      Leaf_a
-    ) should contain (_)}
-    dupMap.makePathless(Top).foreach {Set(Top) should contain (_)}
-    dupMap.makePathless(Middle).foreach {Set(
-      TopCircuit.module("Middle___Top_m1"),
-      TopCircuit.module("Middle___Top_m2"),
-      Middle
-    ) should contain (_)}
-    dupMap.makePathless(Leaf).foreach {Set(
-      TopCircuit.module("Leaf___Top_m1_l1"),
-      TopCircuit.module("Leaf___Top_m2_l1"),
-      TopCircuit.module("Leaf___Middle_l1"),
-      Leaf
-    ) should contain (_) }
+    dupMap.makePathless(Top_m1_l1_a).foreach { Set(TopCircuit.module("Leaf___Top_m1_l1").ref("a")) should contain(_) }
+    dupMap.makePathless(Top_m2_l1_a).foreach { Set(TopCircuit.module("Leaf___Top_m2_l1").ref("a")) should contain(_) }
+    dupMap.makePathless(Top_m1_l2_a).foreach { Set(Leaf_a) should contain(_) }
+    dupMap.makePathless(Top_m2_l2_a).foreach { Set(Leaf_a) should contain(_) }
+    dupMap.makePathless(Middle_l1_a).foreach {
+      Set(
+        TopCircuit.module("Leaf___Top_m1_l1").ref("a"),
+        TopCircuit.module("Leaf___Top_m2_l1").ref("a"),
+        TopCircuit.module("Leaf___Middle_l1").ref("a")
+      ) should contain(_)
+    }
+    dupMap.makePathless(Middle_l2_a).foreach { Set(Leaf_a) should contain(_) }
+    dupMap.makePathless(Leaf_a).foreach {
+      Set(
+        TopCircuit.module("Leaf___Top_m1_l1").ref("a"),
+        TopCircuit.module("Leaf___Top_m2_l1").ref("a"),
+        TopCircuit.module("Leaf___Middle_l1").ref("a"),
+        Leaf_a
+      ) should contain(_)
+    }
+    dupMap.makePathless(Top).foreach { Set(Top) should contain(_) }
+    dupMap.makePathless(Middle).foreach {
+      Set(
+        TopCircuit.module("Middle___Top_m1"),
+        TopCircuit.module("Middle___Top_m2"),
+        Middle
+      ) should contain(_)
+    }
+    dupMap.makePathless(Leaf).foreach {
+      Set(
+        TopCircuit.module("Leaf___Top_m1_l1"),
+        TopCircuit.module("Leaf___Top_m2_l1"),
+        TopCircuit.module("Leaf___Middle_l1"),
+        Leaf
+      ) should contain(_)
+    }
   }
 
   property("Hierarchical donttouch should be resolved properly") {
@@ -159,10 +166,10 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
         |    m2.i <= m1.o
         |
       """.stripMargin
-    canonicalize(outputState.circuit).serialize should be (canonicalize(parse(check)).serialize)
+    canonicalize(outputState.circuit).serialize should be(canonicalize(parse(check)).serialize)
     outputState.annotations.collect {
       case x: DontTouchAnnotation => x.target
-    } should be (Seq(Top.circuitTarget.module("Leaf___Top_m1_l1").ref("a")))
+    } should be(Seq(Top.circuitTarget.module("Leaf___Top_m1_l1").ref("a")))
   }
 
   property("No name conflicts between old and new modules") {
@@ -199,7 +206,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
     val outputState = new LowFirrtlCompiler().compile(inputState, customTransforms)
     val outputLines = outputState.circuit.serialize.split("\n")
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
   }
 
@@ -239,7 +246,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
     val outputLines = outputState.circuit.serialize.split("\n")
 
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
     checks.foreach { line =>
       outputLines should not contain ("  module Middle :")
@@ -267,19 +274,19 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
         |    m2.i <= m1.o
         |    o <= m2.o
       """.stripMargin
-    val e1 = the [CustomTransformException] thrownBy {
+    val e1 = the[CustomTransformException] thrownBy {
       val Top_m1 = Top.instOf("m1", "MiddleX")
       val inputState = CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Top_m1)))
       new LowFirrtlCompiler().compile(inputState, customTransforms)
     }
-    e1.cause shouldBe a [NoSuchTargetException]
+    e1.cause shouldBe a[NoSuchTargetException]
 
-    val e2 = the [CustomTransformException] thrownBy {
+    val e2 = the[CustomTransformException] thrownBy {
       val Top_m2 = Top.instOf("x2", "Middle")
       val inputState = CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Top_m2)))
       new LowFirrtlCompiler().compile(inputState, customTransforms)
     }
-    e2.cause shouldBe a [NoSuchTargetException]
+    e2.cause shouldBe a[NoSuchTargetException]
   }
 
   property("No name conflicts between two new modules") {
@@ -320,11 +327,12 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
         |  module Leaf____Middle__l :""".stripMargin.split("\n")
     val Middle_l1 = CircuitTarget("Top").module("Middle").instOf("_l", "Leaf")
     val Middle_l2 = CircuitTarget("Top").module("Middle_").instOf("l", "Leaf")
-    val inputState = CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Middle_l1), DummyAnnotation(Middle_l2)))
+    val inputState =
+      CircuitState(parse(input), ChirrtlForm, Seq(DummyAnnotation(Middle_l1), DummyAnnotation(Middle_l2)))
     val outputState = new LowFirrtlCompiler().compile(inputState, customTransforms)
     val outputLines = outputState.circuit.serialize.split("\n")
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
   }
 
@@ -362,12 +370,12 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
     val outputState = new VerilogCompiler().compile(inputState, customTransforms)
     val outputLines = outputState.circuit.serialize.split("\n")
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
   }
 
   property("It should remove ResolvePaths annotations") {
-      val input =
+    val input =
       """|circuit Foo:
          |  module Bar:
          |    skip
@@ -378,7 +386,7 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
     CircuitState(passes.ToWorkingIR.run(Parser.parse(input)), UnknownForm, Nil)
       .resolvePaths(Seq(CircuitTarget("Foo").module("Foo").instOf("bar", "Bar")))
       .annotations
-      .collect{ case a: firrtl.annotations.transforms.ResolvePaths => a } should be (empty)
+      .collect { case a: firrtl.annotations.transforms.ResolvePaths => a } should be(empty)
   }
 
   property("It should rename module annotations") {
@@ -404,16 +412,14 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
 
     val parsedCheck = Parser.parse(check)
     info(output.circuit.serialize)
-    (output.circuit.serialize) should be (parsedCheck.serialize)
+    (output.circuit.serialize) should be(parsedCheck.serialize)
 
     val newBar_x = CircuitTarget("Foo").module("Bar___Foo_bar").ref("x")
 
-    output
-      .annotations
-      .filter{
-        case _: DeletedAnnotation => false
-        case _ => true
-      } should contain allOf (DontTouchAnnotation(newBar_x), DontTouchAnnotation(Bar_x))
+    (output.annotations.filter {
+      case _: DeletedAnnotation => false
+      case _ => true
+    } should contain).allOf(DontTouchAnnotation(newBar_x), DontTouchAnnotation(Bar_x))
   }
 
   property("It should not rename lone instances") {
@@ -440,10 +446,10 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
 
     info(output.circuit.serialize)
 
-    output.circuit.serialize should be (inputCircuit.serialize)
-    output.annotations.collect {
+    output.circuit.serialize should be(inputCircuit.serialize)
+    (output.annotations.collect {
       case a: DontTouchAnnotation => a
-    } should contain allOf (
+    } should contain).allOf(
       DontTouchAnnotation(ModuleTarget("Foo", "Foo").ref("foo")),
       DontTouchAnnotation(ModuleTarget("Foo", "Bar").ref("foo")),
       DontTouchAnnotation(ModuleTarget("Foo", "Baz").ref("foo"))
@@ -481,12 +487,12 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
 
     val outputLines = output.circuit.serialize.split("\n")
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
 
-    output.annotations.collect {
+    (output.annotations.collect {
       case a: DontTouchAnnotation => a
-    } should contain allOf (
+    } should contain).allOf(
       DontTouchAnnotation(ModuleTarget("FooBar", "Bar___Foo_bar").ref("baz")),
       DontTouchAnnotation(ModuleTarget("FooBar", "Bar___Foo_barBar").ref("baz"))
     )
@@ -527,11 +533,11 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
 
     val outputLines = output.circuit.serialize.split("\n")
     checks.foreach { line =>
-      outputLines should contain (line)
+      outputLines should contain(line)
     }
-    output.annotations.collect {
+    (output.annotations.collect {
       case a: DontTouchAnnotation => a
-    } should contain allOf (
+    } should contain).allOf(
       DontTouchAnnotation(ModuleTarget("Top", "Baz_0").ref("foo")),
       DontTouchAnnotation(ModuleTarget("Top", "Baz_1").ref("foo"))
     )
@@ -563,11 +569,13 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
 
     info(output.circuit.serialize)
 
-    output.annotations.collect { case a: DontTouchAnnotation => a } should be (Seq(
-      DontTouchAnnotation(ModuleTarget("Top", "Baz___Bar_asdf").ref("foo")),
-      DontTouchAnnotation(ModuleTarget("Top", "Baz___Bar_lkj").ref("foo")),
-      DontTouchAnnotation(baz.ref("foo"))
-    ))
+    output.annotations.collect { case a: DontTouchAnnotation => a } should be(
+      Seq(
+        DontTouchAnnotation(ModuleTarget("Top", "Baz___Bar_asdf").ref("foo")),
+        DontTouchAnnotation(ModuleTarget("Top", "Baz___Bar_lkj").ref("foo")),
+        DontTouchAnnotation(baz.ref("foo"))
+      )
+    )
   }
 
   property("It should properly rename modules with multiple instances") {
@@ -600,6 +608,6 @@ class EliminateTargetPathsSpec extends FirrtlPropSpec with FirrtlMatchers {
     val checkDontTouches = (1 to 4).map { i =>
       DummyAnnotation(ModuleTarget("Top", s"Core___System_core_$i"))
     }
-    output.annotations.collect { case a: DummyAnnotation => a } should be (checkDontTouches)
+    output.annotations.collect { case a: DummyAnnotation => a } should be(checkDontTouches)
   }
 }
diff --git a/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala b/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala
index 2c817c23..54a94edb 100644
--- a/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala
@@ -6,20 +6,20 @@ import firrtl._
 import firrtl.annotations.{JsonProtocol, NoTargetAnnotation}
 import firrtl.ir._
 import firrtl.options.Dependency
-import _root_.logger.{Logger, LogLevel, LogLevelAnnotation}
+import _root_.logger.{LogLevel, LogLevelAnnotation, Logger}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should._
 
 case class AnAnnotation(
-    info: Info,
-    cir: Circuit,
-    mod: DefModule,
-    port: Port,
-    statement: Statement,
-    expr: Expression,
-    tpe: Type,
-    groundType: GroundType
-) extends NoTargetAnnotation
+  info:       Info,
+  cir:        Circuit,
+  mod:        DefModule,
+  port:       Port,
+  statement:  Statement,
+  expr:       Expression,
+  tpe:        Type,
+  groundType: GroundType)
+    extends NoTargetAnnotation
 
 class AnnoInjector extends Transform with DependencyAPIMigration {
   override def optionalPrerequisiteOf = Dependency[ChirrtlEmitter] :: Nil
@@ -51,16 +51,16 @@ class JsonProtocolSpec extends AnyFlatSpec with Matchers {
     val inputAnnos = Seq(AnAnnotation(cir.info, cir, mod, port, stmt, expr, tpe, groundType))
     val annosString = JsonProtocol.serialize(inputAnnos)
     val outputAnnos = JsonProtocol.deserialize(annosString)
-    inputAnnos should be (outputAnnos)
+    inputAnnos should be(outputAnnos)
   }
 
   "Annotation serialization during logging" should "not throw an exception" in {
     val compiler = new firrtl.stage.transforms.Compiler(Seq(Dependency[AnnoInjector]))
     val circuit = Parser.parse("""
-      |circuit test :
-      |  module test :
-      |    output out : UInt<1>
-      |    out <= UInt(0)
+                                 |circuit test :
+                                 |  module test :
+                                 |    output out : UInt<1>
+                                 |    out <= UInt(0)
       """.stripMargin)
     Logger.makeScope(LogLevelAnnotation(LogLevel.Trace) :: Nil) {
       compiler.execute(CircuitState(circuit, Nil))
diff --git a/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala b/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala
index ccf930ba..ac4f2b63 100644
--- a/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala
@@ -16,15 +16,15 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
   }
 
   case class AnAnnotation(
-                           target: Option[CompleteTarget],
-                           from: Option[AnAnnotation] = None,
-                           cause: Option[String] = None
-                         ) extends Annotation {
+    target: Option[CompleteTarget],
+    from:   Option[AnAnnotation] = None,
+    cause:  Option[String] = None)
+      extends Annotation {
     override def update(renames: RenameMap): Seq[AnAnnotation] = {
       if (target.isDefined) {
         renames.get(target.get) match {
-          case None => Seq(this)
-          case Some(Seq()) => Seq(AnAnnotation(None, Some(this)))
+          case None          => Seq(this)
+          case Some(Seq())   => Seq(AnAnnotation(None, Some(this)))
           case Some(targets) =>
             //TODO: Add cause of renaming, requires FIRRTL change to RenameMap
             targets.map { t => AnAnnotation(Some(t), Some(this)) }
@@ -60,7 +60,7 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
       val annotationsx = a.annotations.filter {
         case a: DeletedAnnotation => false
         case AnAnnotation(None, _, _) => false
-        case _: DupedResult => false
+        case _: DupedResult   => false
         case _: DedupedResult => false
         case _ => true
       }
@@ -296,8 +296,7 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
       )
   }
 
-
-  behavior of "EliminateTargetPaths"
+  behavior.of("EliminateTargetPaths")
 
   // NOTE: equivalience is defined structurally in this case
   trait RightInverseEliminateTargetsFixture extends RightInverseFixture with DefaultExample {
@@ -393,24 +392,29 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
          |    inst qux of Baz___Top_qux""".stripMargin
     override val annotations: AnnotationSeq = Seq(
       AnAnnotation(CircuitTarget("Top").module("Baz").instOf("foo", "Foo")),
-      ResolvePaths(Seq(
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foox", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("bar", "Bar"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foox", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("bar", "Bar")
-      ))
+      ResolvePaths(
+        Seq(
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foox", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("bar", "Bar"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foox", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("bar", "Bar")
+        )
+      )
     )
 
-    override val finalAnnotations: Option[AnnotationSeq] = Some(Seq(
-      AnAnnotation(CircuitTarget("Top").module("Foo___Top_qux_foo")),
-      AnAnnotation(CircuitTarget("Top").module("Foo___Top_baz_foo"))
-    ))
+    override val finalAnnotations: Option[AnnotationSeq] = Some(
+      Seq(
+        AnAnnotation(CircuitTarget("Top").module("Foo___Top_qux_foo")),
+        AnAnnotation(CircuitTarget("Top").module("Foo___Top_baz_foo"))
+      )
+    )
     test()
   }
 
   it should "be idempotent with per-module annotations" in new IdempotencyEliminateTargetsFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allModuleInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
@@ -418,6 +422,7 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
   }
 
   it should "be idempotent with per-instance annotations" in new IdempotencyEliminateTargetsFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allAbsoluteInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
@@ -425,13 +430,14 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
   }
 
   it should "be idempotent with relative module annotations" in new IdempotencyEliminateTargetsFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allRelative2LevelInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
     test()
   }
 
-  behavior of "DedupModules"
+  behavior.of("DedupModules")
 
   trait RightInverseDedupModulesFixture extends RightInverseFixture with DefaultExample {
     override val f: Seq[Transform] = Seq(new firrtl.annotations.transforms.EliminateTargetPaths)
@@ -498,24 +504,29 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
          |    inst qux of Baz""".stripMargin
     override val annotations: AnnotationSeq = Seq(
       AnAnnotation(CircuitTarget("Top").module("Baz").instOf("foo", "Foo")),
-      ResolvePaths(Seq(
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foox", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("bar", "Bar"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foox", "Foo"),
-        CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("bar", "Bar")
-      ))
+      ResolvePaths(
+        Seq(
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foox", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("bar", "Bar"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foox", "Foo"),
+          CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("bar", "Bar")
+        )
+      )
     )
 
-    override val finalAnnotations: Option[AnnotationSeq] = Some(Seq(
-      AnAnnotation(CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo")),
-      AnAnnotation(CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"))
-    ))
+    override val finalAnnotations: Option[AnnotationSeq] = Some(
+      Seq(
+        AnAnnotation(CircuitTarget("Top").module("Top").instOf("baz", "Baz").instOf("foo", "Foo")),
+        AnAnnotation(CircuitTarget("Top").module("Top").instOf("qux", "Baz").instOf("foo", "Foo"))
+      )
+    )
     test()
   }
 
   it should "be idempotent with per-module annotations" in new IdempotencyDedupModulesFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allModuleInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
@@ -523,6 +534,7 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
   }
 
   it should "be idempotent with per-instance annotations" in new IdempotencyDedupModulesFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allAbsoluteInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
@@ -530,6 +542,7 @@ class MorphismSpec extends AnyFlatSpec with Matchers {
   }
 
   it should "be idempotent with relative module annotations" in new IdempotencyDedupModulesFixture {
+
     /** An endomorphism */
     override val annotations: AnnotationSeq =
       allRelative2LevelInstances.map(AnAnnotation.apply) :+ ResolvePaths(allAbsoluteInstances)
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
index cbcd72e9..cc875ea1 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala
@@ -11,7 +11,6 @@ import firrtl.annotations.{Annotation, NoTargetAnnotation}
 case object FoundTargetDirTransformRanAnnotation extends NoTargetAnnotation
 case object FoundTargetDirTransformFoundTargetDirAnnotation extends NoTargetAnnotation
 
-
 /** Looks for [[TargetDirAnnotation]] */
 class FindTargetDirTransform extends Transform {
   def inputForm = HighForm
@@ -19,14 +18,15 @@ class FindTargetDirTransform extends Transform {
 
   def execute(state: CircuitState): CircuitState = {
     val a: Option[Annotation] = state.annotations.collectFirst {
-      case TargetDirAnnotation("a/b/c") => FoundTargetDirTransformFoundTargetDirAnnotation }
+      case TargetDirAnnotation("a/b/c") => FoundTargetDirTransformFoundTargetDirAnnotation
+    }
     state.copy(annotations = state.annotations ++ a ++ Some(FoundTargetDirTransformRanAnnotation))
   }
 }
 
 class TargetDirAnnotationSpec extends FirrtlFlatSpec {
 
-  behavior of "The target directory"
+  behavior.of("The target directory")
 
   val input =
     """circuit Top :
@@ -41,37 +41,35 @@ class TargetDirAnnotationSpec extends FirrtlFlatSpec {
     val findTargetDir = new FindTargetDirTransform // looks for the annotation
 
     val optionsManager = new ExecutionOptionsManager("TargetDir") with HasFirrtlOptions {
-      commonOptions = commonOptions.copy(targetDirName = targetDir,
-                                         topName = "Top")
-      firrtlOptions = firrtlOptions.copy(compilerName = "high",
-                                         firrtlSource = Some(input),
-                                         customTransforms = Seq(findTargetDir))
+      commonOptions = commonOptions.copy(targetDirName = targetDir, topName = "Top")
+      firrtlOptions =
+        firrtlOptions.copy(compilerName = "high", firrtlSource = Some(input), customTransforms = Seq(findTargetDir))
     }
     val annotations: Seq[Annotation] = Driver.execute(optionsManager) match {
       case a: FirrtlExecutionSuccess => a.circuitState.annotations
       case _ => fail
     }
 
-    annotations should contain (FoundTargetDirTransformRanAnnotation)
-    annotations should contain (FoundTargetDirTransformFoundTargetDirAnnotation)
+    annotations should contain(FoundTargetDirTransformRanAnnotation)
+    annotations should contain(FoundTargetDirTransformFoundTargetDirAnnotation)
 
     // Delete created directory
     val dir = new java.io.File(targetDir)
-    dir.exists should be (true)
-    FileUtils.deleteDirectoryHierarchy("a") should be (true)
+    dir.exists should be(true)
+    FileUtils.deleteDirectoryHierarchy("a") should be(true)
   }
 
   it should "NOT be available as an annotation when using a raw compiler" in {
     val findTargetDir = new FindTargetDirTransform // looks for the annotation
     val compiler = new VerilogCompiler
-    val circuit = Parser.parse(input split "\n")
+    val circuit = Parser.parse(input.split("\n"))
 
     val annotations: Seq[Annotation] = compiler
       .compileAndEmit(CircuitState(circuit, HighForm), Seq(findTargetDir))
       .annotations
 
     // Check that FindTargetDirTransform does not find the annotation
-    annotations should contain (FoundTargetDirTransformRanAnnotation)
+    annotations should contain(FoundTargetDirTransformRanAnnotation)
     annotations should not contain (FoundTargetDirTransformFoundTargetDirAnnotation)
   }
 }
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index 641eeb99..48f27faa 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -24,8 +24,9 @@ class TargetSpec extends FirrtlPropSpec {
         (top.ref("r").index(1).field("hi").clock, "~Circuit|Top>r[1].hi@clock"),
         (GenericTarget(None, None, Vector(Ref("r"))), "~???|???>r")
       )
-    targets.foreach { case (t, str) =>
-      assert(t.serialize == str, s"$t does not properly serialize")
+    targets.foreach {
+      case (t, str) =>
+        assert(t.serialize == str, s"$t does not properly serialize")
     }
   }
   property("Should convert to/from Named") {
@@ -38,7 +39,7 @@ class TargetSpec extends FirrtlPropSpec {
     check(Target(Some("Top"), Some("Top"), r2))
   }
   property("Should enable creating from API") {
-    val top = ModuleTarget("Top","Top")
+    val top = ModuleTarget("Top", "Top")
     val x_reg0_data = top.instOf("x", "X").ref("reg0").field("data")
     top.instOf("x", "x")
     top.ref("y")
@@ -47,8 +48,14 @@ class TargetSpec extends FirrtlPropSpec {
     val circuit = CircuitTarget("Circuit")
     val top = circuit.module("Top")
     val targets: Seq[Target] =
-      Seq(circuit, top, top.instOf("i", "I"), top.ref("r"),
-        top.ref("r").index(1).field("hi").clock, GenericTarget(None, None, Vector(Ref("r"))))
+      Seq(
+        circuit,
+        top,
+        top.instOf("i", "I"),
+        top.ref("r"),
+        top.ref("r").index(1).field("hi").clock,
+        GenericTarget(None, None, Vector(Ref("r")))
+      )
     targets.foreach { t =>
       assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize")
     }
@@ -58,25 +65,20 @@ class TargetSpec extends FirrtlPropSpec {
     val top = circuit.module("B")
     val targets = Seq(
       (circuit, "circuit A:"),
-      (top,
-       """|circuit A:
-          |└── module B:""".stripMargin),
-      (top.instOf("c", "C"),
-       """|circuit A:
-          |└── module B:
-          |    └── inst c of C:""".stripMargin),
-      (top.ref("r"),
-       """|circuit A:
-          |└── module B:
-          |    └── r""".stripMargin),
-      (top.ref("r").index(1).field("hi").clock,
-       """|circuit A:
-          |└── module B:
-          |    └── r[1].hi@clock""".stripMargin),
-      (GenericTarget(None, None, Vector(Ref("r"))),
-       """|circuit ???:
-          |└── module ???:
-          |    └── r""".stripMargin)
+      (top, """|circuit A:
+              |└── module B:""".stripMargin),
+      (top.instOf("c", "C"), """|circuit A:
+                               |└── module B:
+                               |    └── inst c of C:""".stripMargin),
+      (top.ref("r"), """|circuit A:
+                       |└── module B:
+                       |    └── r""".stripMargin),
+      (top.ref("r").index(1).field("hi").clock, """|circuit A:
+                                                  |└── module B:
+                                                  |    └── r[1].hi@clock""".stripMargin),
+      (GenericTarget(None, None, Vector(Ref("r"))), """|circuit ???:
+                                                      |└── module ???:
+                                                      |    └── r""".stripMargin)
     )
     targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") }
   }