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authorKevin Laeufer2023-01-25 11:06:45 -0500
committerGitHub2023-01-25 16:06:45 +0000
commit82af22f300a6d47c63cd3304d5c9d0447b33091a (patch)
treec1eca36fdebed0ffa362a0d44295ab3352afcf27 /src/test/scala/firrtlTests/SerializerSpec.scala
parent59f62d82f28947af472fc8ed030051be40f5bfbe (diff)
[smem] fix read-under-write serialization (#2595)
* [smem] fix read-under-write serialization Also adds some tests for the parser and the serializer. * Serializer: always serialize smem ruw behavior * test: simplify smem test circuit
Diffstat (limited to 'src/test/scala/firrtlTests/SerializerSpec.scala')
-rw-r--r--src/test/scala/firrtlTests/SerializerSpec.scala15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/SerializerSpec.scala b/src/test/scala/firrtlTests/SerializerSpec.scala
index 9a984d60..0e72b97f 100644
--- a/src/test/scala/firrtlTests/SerializerSpec.scala
+++ b/src/test/scala/firrtlTests/SerializerSpec.scala
@@ -121,4 +121,19 @@ class SerializerSpec extends AnyFlatSpec with Matchers {
val serialized = Serializer.serialize(when, 1)
serialized should be(" when cond :\n skip\n")
}
+
+ it should "serialize read-under-write behavior for smems correctly" in {
+ def parseSerializeParse(src: String): Circuit = Parser.parse(Parser.parse(src).serialize)
+ val undefined = parseSerializeParse(SMemTestCircuit.src(""))
+ assert(SMemTestCircuit.findRuw(undefined) == ReadUnderWrite.Undefined)
+
+ val undefined2 = parseSerializeParse(SMemTestCircuit.src(" undefined"))
+ assert(SMemTestCircuit.findRuw(undefined2) == ReadUnderWrite.Undefined)
+
+ val old = parseSerializeParse(SMemTestCircuit.src(" old"))
+ assert(SMemTestCircuit.findRuw(old) == ReadUnderWrite.Old)
+
+ val readNew = parseSerializeParse(SMemTestCircuit.src(" new"))
+ assert(SMemTestCircuit.findRuw(readNew) == ReadUnderWrite.New)
+ }
}