[smem] fix read-under-write serialization (#2595)

* [smem] fix read-under-write serialization

Also adds some tests for the parser and
the serializer.

* Serializer: always serialize smem ruw behavior

* test: simplify smem test circuit

1 files changed, 29 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 5003871d..dea44844 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -405,6 +405,35 @@ class ParserSpec extends FirrtlFlatSpec {
       firrtl.Parser.parse(input)
     }
   }
+
+  it should "parse smem read-under-write behavior" in {
+    val undefined = firrtl.Parser.parse(SMemTestCircuit.src(""))
+    assert(SMemTestCircuit.findRuw(undefined) == ReadUnderWrite.Undefined)
+
+    val undefined2 = firrtl.Parser.parse(SMemTestCircuit.src(" undefined"))
+    assert(SMemTestCircuit.findRuw(undefined2) == ReadUnderWrite.Undefined)
+
+    val old = firrtl.Parser.parse(SMemTestCircuit.src(" old"))
+    assert(SMemTestCircuit.findRuw(old) == ReadUnderWrite.Old)
+
+    val readNew = firrtl.Parser.parse(SMemTestCircuit.src(" new"))
+    assert(SMemTestCircuit.findRuw(readNew) == ReadUnderWrite.New)
+  }
+}
+
+/** used to test parsing and serialization of smems */
+object SMemTestCircuit {
+  def src(ruw: String): String =
+    s"""circuit Example :
+       |  module Example :
+       |    smem mem : UInt<8> [8] $ruw@[main.scala 10:25]
+       |""".stripMargin
+
+  def findRuw(c: Circuit): ReadUnderWrite.Value = {
+    val main = c.modules.head.asInstanceOf[ir.Module]
+    val mem = main.body.asInstanceOf[ir.Block].stmts.collectFirst { case m: CDefMemory => m }.get
+    mem.readUnderWrite
+  }
 }
 
 class ParserPropSpec extends FirrtlPropSpec {