Allow Side Effecting Statement to have Names (#2057)

* firrtl: add optional statement labels for stop, printf, assert, assume and cover

* test: parsing of statement labels

* ir: ensure that name is properly retained

* SymbolTable: add support for labled statements

* test: parsing statement labels

* test: lower types name collisions with named statements

* ignore empty names

* Inline: deal with named and unnamed statements

* RemoveWires: treat stop, printf and verification statements as "others"

* test: fix InlineInstance tests

* DeadCodeEliminations: statements are now als declarations

* CheckHighForm: ensure that statement names are not used as references

* CheckSpec: throw error if statement name collides

* add pass to automatically add missing statement names

* check: make sure that two statements cannot have the same name

* stmtLabel -> stmtName

* scalafmt

* add statement names to spec

* spec: meta data -> metadata

* EnsureStatementNames: explain naming algorithm

* remove returns

* better namespace use

* ir: add CanBeReferenced trait

* ir: add newline as jack requested

1 files changed, 21 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 373b960c..ba61b134 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -147,6 +147,27 @@ class ParserSpec extends FirrtlFlatSpec {
     }
   }
 
+  // ********** Statement labels **********
+  it should "allow certain statement to have a label" in {
+    val prelude = Seq("circuit top :", "  module top :", "    input c : Clock")
+    val statements = Seq("stop(c, UInt(1), 0)", "printf(c, UInt(1), \"\")") ++
+      Seq("assert", "assume", "cover").map(_ + "(c, UInt(1), UInt(1), \"\")")
+    val validLabels = Seq(":test" -> "test", " :test" -> "test", " : test" -> "test", " : test01" -> "test01")
+    statements.foreach { stmt =>
+      validLabels.foreach {
+        case (lbl, expected) =>
+          val line = "    " + stmt + lbl
+          val src = (prelude :+ line).mkString("\n") + "\n"
+          val res = firrtl.Parser.parse(src)
+          CircuitState(res, Nil) should containTree {
+            case s: Stop         => s.name == expected
+            case s: Print        => s.name == expected
+            case s: Verification => s.name == expected
+          }
+      }
+    }
+  }
+
   // ********** Keywords **********
   "Keywords" should "be allowed as Ids" in {
     import KeywordTests._