diff options
| author | Schuyler Eldridge | 2020-04-22 19:55:32 -0400 |
|---|---|---|
| committer | GitHub | 2020-04-22 19:55:32 -0400 |
| commit | 65360f886f9b92438d1b6fe609120b34ebb413cf (patch) | |
| tree | 073ebe73d43e652af1f71a08d34cc30a421c4dbb /src/test/scala/firrtlTests/InferReadWriteSpec.scala | |
| parent | 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 (diff) | |
| parent | 184d40095179a9f49dd21e73e2c02b998bac5c00 (diff) | |
Merge pull request #1534 from freechipsproject/deprecate-transform-2
Trait-base Dependency API Migration
Diffstat (limited to 'src/test/scala/firrtlTests/InferReadWriteSpec.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/InferReadWriteSpec.scala | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 9913a7c1..4268bd2b 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -4,7 +4,9 @@ package firrtlTests import firrtl._ import firrtl.ir._ +import firrtl.options.PreservesAll import firrtl.passes._ +import firrtl.stage.Forms import firrtl.testutils._ import firrtl.testutils.FirrtlCheckers._ @@ -12,9 +14,11 @@ class InferReadWriteSpec extends SimpleTransformSpec { class InferReadWriteCheckException extends PassException( "Readwrite ports are not found!") - object InferReadWriteCheck extends Pass { - override def inputForm = MidForm - override def outputForm = MidForm + object InferReadWriteCheck extends Pass with PreservesAll[Transform] { + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters + def findReadWrite(s: Statement): Boolean = s match { case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 => s.name == "mem" && s.readwriters.head == "rw" |
