From 39d76a02785f4391b67abd3b7d7720d287736312 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 21 Apr 2020 22:41:23 -0400 Subject: Mixin DependencyAPIMigration to all Transforms This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/InferReadWriteSpec.scala | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src/test/scala/firrtlTests/InferReadWriteSpec.scala') diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 9913a7c1..4268bd2b 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -4,7 +4,9 @@ package firrtlTests import firrtl._ import firrtl.ir._ +import firrtl.options.PreservesAll import firrtl.passes._ +import firrtl.stage.Forms import firrtl.testutils._ import firrtl.testutils.FirrtlCheckers._ @@ -12,9 +14,11 @@ class InferReadWriteSpec extends SimpleTransformSpec { class InferReadWriteCheckException extends PassException( "Readwrite ports are not found!") - object InferReadWriteCheck extends Pass { - override def inputForm = MidForm - override def outputForm = MidForm + object InferReadWriteCheck extends Pass with PreservesAll[Transform] { + override def prerequisites = Forms.MidForm + override def optionalPrerequisites = Seq.empty + override def dependents = Forms.MidEmitters + def findReadWrite(s: Statement): Boolean = s match { case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 => s.name == "mem" && s.readwriters.head == "rw" -- cgit v1.2.3