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| author | John Ingalls | 2020-01-06 18:47:19 -0800 |
|---|---|---|
| committer | Jack Koenig | 2020-01-06 18:47:19 -0800 |
| commit | f77487d37bd7c61be231a8000a3197d37cf55499 (patch) | |
| tree | 99208af73baad6fef176ce86d14a17e790e15d10 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | dcf0076ca9b4b3c094d2d082717265fb4e326ae0 (diff) | |
Verilog emitter transform InlineNots (#1270)
[skip formal checks]
* ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false
* transform InlineNots
* transform back-to-back Nots into straight rename
* swap mux with inverted select
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
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