diff options
| author | Jack Koenig | 2020-08-15 10:16:28 -0700 |
|---|---|---|
| committer | GitHub | 2020-08-15 10:16:28 -0700 |
| commit | f1c314e6c7e116df33ffc215ec907212037292dc (patch) | |
| tree | f06060e9fb52f4f5b30bc56db78acb6bd371642d /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 2e5f942d25d7afab79ee1263c5d6833cad9d743d (diff) | |
| parent | 9adbe1ede59f9aeb25e71fd8318a4e7e46c4cc34 (diff) | |
Merge pull request #1852 from freechipsproject/format-src-4
Apply Scalafmt Rewriting
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
| -rw-r--r-- | src/test/scala/firrtlTests/ExtModuleTests.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/ExtModuleTests.scala b/src/test/scala/firrtlTests/ExtModuleTests.scala index 9ab3429e..5a58df2b 100644 --- a/src/test/scala/firrtlTests/ExtModuleTests.scala +++ b/src/test/scala/firrtlTests/ExtModuleTests.scala @@ -20,7 +20,6 @@ class ExtModuleTests extends FirrtlFlatSpec { | parameter TYP = 'bit' | """.stripMargin val parsed = parse(input) - (parse(parsed.serialize)) should be (parsed) + (parse(parsed.serialize)) should be(parsed) } } - |