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| author | Jack Koenig | 2019-10-30 22:38:45 -0700 |
|---|---|---|
| committer | Jack Koenig | 2019-10-31 13:44:52 -0700 |
| commit | 28ffacca906c688f01454c4e24768572613e2d00 (patch) | |
| tree | 0cb3be00efe5f48d3bf2d10ff685122b035a4774 /src/test/scala/firrtlTests/ExtModuleTests.scala | |
| parent | 68964fed765cd037f3db362a07d4a9ae48c38900 (diff) | |
Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleTests.scala')
0 files changed, 0 insertions, 0 deletions