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| author | Angie Wang | 2016-10-23 19:32:18 -0700 |
|---|---|---|
| committer | Donggyu | 2016-10-23 19:32:18 -0700 |
| commit | de45e93c43201c5b757d681fb922a57564462a08 (patch) | |
| tree | 0593b4e4d846ab2a205ca7ef4f6f66606775c023 /src/test/scala/firrtlTests/ExtModuleSpec.scala | |
| parent | bcf73fb70969e5629a693c18f1f2ee7b37f14a76 (diff) | |
Fix bitmask (#346)
* toBitMask cat direction should be consistent with data
* minor comment updates
* moved remaining mem passes/utils to memlib
* changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleSpec.scala')
0 files changed, 0 insertions, 0 deletions