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| author | Albert Magyar | 2020-09-04 13:00:14 -0700 |
|---|---|---|
| committer | GitHub | 2020-09-04 13:00:14 -0700 |
| commit | b25c90f27bcf5ff61d7f0d16fb274759a628a500 (patch) | |
| tree | a5f0d18c40a33151f4eaddec86307532929f90c7 /src/test/scala/firrtlTests/ExtModuleSpec.scala | |
| parent | 3b12706287bfbb07cff09a101aab1abedb522858 (diff) | |
| parent | 8dbecda01a4d9b400f89cb5c858352d763365f51 (diff) | |
Merge pull request #1883 from freechipsproject/legalize-mem-clocks
Legalize mem port clocks to avoid Verilator-unfriendly sensitivity lists
Diffstat (limited to 'src/test/scala/firrtlTests/ExtModuleSpec.scala')
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