All of src/ formatted with scalafmt

1 files changed, 12 insertions, 11 deletions

diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index b309467a..a9084f0b 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -13,7 +13,8 @@ import java.io.File
 import java.nio.file.Paths
 
 case class AnnotationWithDontTouches(target: ReferenceTarget)
-    extends SingleTargetAnnotation[ReferenceTarget] with HasDontTouches {
+    extends SingleTargetAnnotation[ReferenceTarget]
+    with HasDontTouches {
   def targets = Seq(target)
   def duplicate(n: ReferenceTarget) = this.copy(n)
   def dontTouches: Seq[ReferenceTarget] = targets
@@ -31,9 +32,9 @@ class DCETests extends FirrtlFlatSpec {
     val finalState = (new LowFirrtlCompiler).compileAndEmit(state, customTransforms)
     val res = finalState.getEmittedCircuit.value
     // Convert to sets for comparison
-    val resSet = Set(parse(res).serialize.split("\n"):_*)
-    val checkSet = Set(parse(check).serialize.split("\n"):_*)
-    resSet should be (checkSet)
+    val resSet = Set(parse(res).serialize.split("\n"): _*)
+    val checkSet = Set(parse(check).serialize.split("\n"): _*)
+    resSet should be(checkSet)
   }
 
   "Unread wire" should "be deleted" in {
@@ -418,7 +419,7 @@ class DCETests extends FirrtlFlatSpec {
     exec(input, check)
   }
   // This currently does NOT work
-  behavior of "Single dead instances"
+  behavior.of("Single dead instances")
   ignore should "should be deleted" in {
     val input =
       """circuit Top :
@@ -469,9 +470,9 @@ class DCETests extends FirrtlFlatSpec {
     val result = (new VerilogCompiler).compileAndEmit(state, List.empty)
     val verilog = result.getEmittedCircuit.value
     // Check that mux is removed!
-    verilog shouldNot include regex ("""a \? x : r;""")
+    (verilog shouldNot include).regex("""a \? x : r;""")
     // Check for register update
-    verilog should include regex ("""(?m)if \(a\) begin\n\s*r <= x;\s*end""")
+    (verilog should include).regex("""(?m)if \(a\) begin\n\s*r <= x;\s*end""")
   }
 
   "Emitted Verilog" should "not contain dead print or stop statements" in {
@@ -487,8 +488,8 @@ class DCETests extends FirrtlFlatSpec {
     val state = CircuitState(input, ChirrtlForm)
     val result = (new VerilogCompiler).compileAndEmit(state, List.empty)
     val verilog = result.getEmittedCircuit.value
-    verilog shouldNot include regex ("""fwrite""")
-    verilog shouldNot include regex ("""fatal""")
+    (verilog shouldNot include).regex("""fwrite""")
+    (verilog shouldNot include).regex("""fatal""")
   }
 }
 
@@ -502,7 +503,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec {
   "Dead Code Elimination" should "run by default" in {
     firrtl.Driver.execute(args) match {
       case FirrtlExecutionSuccess(_, verilog) =>
-        verilog should not include regex ("wire +a")
+        (verilog should not).include(regex("wire +a"))
       case _ => fail("Unexpected compilation failure")
     }
   }
@@ -510,7 +511,7 @@ class DCECommandLineSpec extends FirrtlFlatSpec {
   it should "not run when given --no-dce option" in {
     firrtl.Driver.execute(args :+ "--no-dce") match {
       case FirrtlExecutionSuccess(_, verilog) =>
-        verilog should include regex ("wire +a")
+        (verilog should include).regex("wire +a")
       case _ => fail("Unexpected compilation failure")
     }
   }