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authorJack Koenig2017-12-20 13:18:33 -0800
committerGitHub2017-12-20 13:18:33 -0800
commit4801d9cbc3cd957496daa00b099ead15f9f4e17d (patch)
treeec92d7648107c8c79c4c3035aa9b684db461d30c /src/test/scala/firrtlTests/DCETests.scala
parente3ea1000d4e4cce40fb7f583a55f4bd30115eb5d (diff)
Make submodule inputs void in ExpandWhens (#706)
Diffstat (limited to 'src/test/scala/firrtlTests/DCETests.scala')
-rw-r--r--src/test/scala/firrtlTests/DCETests.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index d1848ab8..e28ab432 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -117,6 +117,7 @@ class DCETests extends FirrtlFlatSpec {
| output z : UInt<1>
| inst sub of Sub
| sub.x <= x
+ | sub.y is invalid
| z <= sub.z""".stripMargin
val check =
"""circuit Top :