From 4801d9cbc3cd957496daa00b099ead15f9f4e17d Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Dec 2017 13:18:33 -0800
Subject: Make submodule inputs void in ExpandWhens (#706)

---
 src/test/scala/firrtlTests/DCETests.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/test/scala/firrtlTests/DCETests.scala')

diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index d1848ab8..e28ab432 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -117,6 +117,7 @@ class DCETests extends FirrtlFlatSpec {
         |    output z : UInt<1>
         |    inst sub of Sub
         |    sub.x <= x
+        |    sub.y is invalid
         |    z <= sub.z""".stripMargin
     val check =
       """circuit Top :
-- 
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