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authorJack Koenig2017-11-09 19:02:43 -0800
committerJack Koenig2017-12-12 15:34:43 -0800
commite39609a2bfbbd108fa1e5044e9c270685d75a816 (patch)
tree3f773ec4197c4a2ec9969c6e75db16afffe57f51 /src/test/scala/firrtlTests/ConstantPropagationTests.scala
parent7cc075438aa8b67fb52f0556ac9a5bc07bcca232 (diff)
Add RemoveWires transform
This transform replaces all wires with nodes in a legal, flow-forward order
Diffstat (limited to 'src/test/scala/firrtlTests/ConstantPropagationTests.scala')
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index e7bf7884..06e24b97 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -721,7 +721,13 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
| wire z : UInt<1>
| y <= z
| z <= x""".stripMargin
- val check = input
+ val check =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | output y : UInt<1>
+ | node z = x
+ | y <= z""".stripMargin
execute(input, check, Seq(dontTouch("Top.z")))
}