Merge pull request #898 from seldridge/port-uniqueness-checks

Enforce port uniqueness in Chirrtl/High Checks

1 files changed, 28 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 3c9894ba..767f2392 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -282,4 +282,32 @@ class CheckSpec extends FlatSpec with Matchers {
       }
     }
   }
+
+  behavior of "Uniqueness"
+  for ((description, input) <- CheckSpec.nonUniqueExamples) {
+    it should s"be asserted for $description" in {
+      assertThrows[CheckHighForm.NotUniqueException] {
+        Seq(ToWorkingIR, CheckHighForm).foldLeft(Parser.parse(input)){ case (c, tx) => tx.run(c) }
+      }
+    }
+  }
 }
+
+object CheckSpec {
+  val nonUniqueExamples = List(
+    ("two ports with the same name",
+     """|circuit Top:
+        |  module Top:
+        |    input a: UInt<1>
+        |    input a: UInt<1>""".stripMargin),
+    ("two nodes with the same name",
+     """|circuit Top:
+        |  module Top:
+        |    node a = UInt<1>("h0")
+        |    node a = UInt<1>("h0")""".stripMargin),
+    ("a port and a node with the same name",
+     """|circuit Top:
+        |  module Top:
+        |    input a: UInt<1>
+        |    node a = UInt<1>("h0") """.stripMargin) )
+  }