DRY check chirrtl (#1148)

* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks

* Add test case for illegal Chirrtl memory in HighForm

1 files changed, 27 insertions, 53 deletions

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index af16ec03..93bc2cab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -2,18 +2,32 @@
 
 package firrtlTests
 
-import java.io._
 import org.scalatest._
-import org.scalatest.prop._
 import firrtl.{Parser, CircuitState, UnknownForm, Transform}
 import firrtl.ir.Circuit
 import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders}
 
 class CheckSpec extends FlatSpec with Matchers {
+  val defaultPasses = Seq(ToWorkingIR, CheckHighForm)
+  def checkHighInput(input: String) = {
+    defaultPasses.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+  }
+
+  "CheckHighForm" should "disallow Chirrtl-style memories" in {
+    val input =
+      """circuit foo :
+        |  module foo :
+        |    input clock : Clock
+        |    input addr : UInt<2>
+        |    smem mem : UInt<1>[4]""".stripMargin
+    intercept[CheckHighForm.IllegalChirrtlMemException] {
+      checkHighInput(input)
+    }
+  }
+
   "Memories with flip in the data type" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -23,16 +37,11 @@ class CheckSpec extends FlatSpec with Matchers {
         |      read-latency => 0
         |      write-latency => 1""".stripMargin
     intercept[CheckHighForm.MemWithFlipException] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }
 
   "Registers with flip in the type" should "throw an exception" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """circuit Unit :
         |  module Unit :
@@ -42,16 +51,11 @@ class CheckSpec extends FlatSpec with Matchers {
         |    reg r : {a : UInt<32>, flip b : UInt<32>}, clk
         |    out <= in""".stripMargin
     intercept[CheckHighForm.RegWithFlipException] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }
 
   "Instance loops a -> b -> a" should "be detected" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """
         |circuit Foo :
@@ -70,16 +74,11 @@ class CheckSpec extends FlatSpec with Matchers {
         |    b <= foo.b
       """.stripMargin
     intercept[CheckHighForm.InstanceLoop] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }
 
   "Instance loops a -> b -> c -> a" should "be detected" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """
         |circuit Dog :
@@ -105,16 +104,11 @@ class CheckSpec extends FlatSpec with Matchers {
         |    b <= foo.b
         |      """.stripMargin
     intercept[CheckHighForm.InstanceLoop] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }
 
   "Instance loops a -> a" should "be detected" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """
         |circuit Apple :
@@ -126,16 +120,11 @@ class CheckSpec extends FlatSpec with Matchers {
         |    b <= recurse_foo.b
         |      """.stripMargin
     intercept[CheckHighForm.InstanceLoop] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }
 
   "Instance loops should not have false positives" should "be detected" in {
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm)
     val input =
       """
         |circuit Hammer :
@@ -158,10 +147,7 @@ class CheckSpec extends FlatSpec with Matchers {
         |    output b : UInt<32>
         |    b <= a
         |      """.stripMargin
-    passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-      (c: Circuit, p: Pass) => p.run(c)
-    }
-
+    checkHighInput(input)
   }
 
   "Clock Types" should "be connectable" in {
@@ -264,10 +250,6 @@ class CheckSpec extends FlatSpec with Matchers {
 
   for (op <- List("shl", "shr")) {
     s"$op by negative amount" should "result in an error" in {
-      val passes = Seq(
-        ToWorkingIR,
-        CheckHighForm
-      )
       val amount = -1
       val input =
         s"""circuit Unit :
@@ -276,9 +258,7 @@ class CheckSpec extends FlatSpec with Matchers {
            |    output z: UInt
            |    z <= $op(x, $amount)""".stripMargin
       val exception = intercept[PassException] {
-        passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-          (c: Circuit, p: Pass) => p.run(c)
-        }
+        checkHighInput(input)
       }
       exception.getMessage should include (s"Primop $op argument $amount < 0")
     }
@@ -292,14 +272,8 @@ class CheckSpec extends FlatSpec with Matchers {
          |    output foo : UInt
          |    foo <= bits(in, 3, 4)
          |      """.stripMargin
-    val passes = Seq(
-      ToWorkingIR,
-      CheckHighForm
-    )
     val exception = intercept[PassException] {
-      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
-        (c: Circuit, p: Pass) => p.run(c)
-      }
+      checkHighInput(input)
     }
   }