Reworked annotation system. Added tenacity and permissibility

Conflicts:
	src/main/scala/firrtl/Compiler.scala
	src/main/scala/firrtl/LoweringCompilers.scala
	src/main/scala/firrtl/passes/Inline.scala
	src/test/scala/firrtlTests/AnnotationTests.scala
	src/test/scala/firrtlTests/InlineInstancesTests.scala

1 files changed, 62 insertions, 34 deletions

diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index e04b4e14..0312df5d 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -1,58 +1,86 @@
 package firrtlTests
 
-import java.io.StringWriter
+import java.io.{Writer, StringWriter}
 
 import org.scalatest.FlatSpec
 import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
 import firrtl.ir.Circuit
+import firrtl.Parser
 import firrtl.{
-   Parser,
+   ResolveAndCheck,
+   RenameMap,
+   Compiler,
+   CompilerResult,
+   VerilogCompiler
+}
+import firrtl.Annotations.{
+   TransID,
    Named,
+   CircuitName,
    ModuleName,
    ComponentName,
-   CircuitAnnotation,
-   StringAnnotation,
-   BrittleCircuitAnnotation,
-   UnknownCAKind,
-   Compiler,
-   CompilerResult,
+   AnnotationException,
    Annotation,
-   RenameMap,
-   VerilogCompiler
+   Strict,
+   Rigid,
+   Firm,
+   Loose,
+   Sticky,
+   Insistent,
+   Fickle,
+   Unstable,
+   AnnotationMap
 }
 
 /**
  * An example methodology for testing Firrtl annotations.
  */
-abstract class AnnotationSpec extends FlatSpec {
-   def parse (s: String): Circuit = Parser.parse(s.split("\n").toIterator)
-   def compiler: Compiler
-   def input: String
-   def getResult (annotation: CircuitAnnotation): CompilerResult = {
-      val writer = new StringWriter()
-      compiler.compile(parse(input), Seq(annotation), writer)
-   }
+trait AnnotationSpec extends LowTransformSpec {
+  // Dummy transform
+  def transform = new ResolveAndCheck()
+
+  // Check if Annotation Exception is thrown
+  override def failingexecute(writer: Writer, annotations: AnnotationMap, input: String) = {
+    intercept[AnnotationException] {
+      compile(parse(input), annotations, writer)
+    }
+  }
+  def execute(writer: Writer, annotations: AnnotationMap, input: String, check: Annotation) = {
+    val cr = compile(parse(input), annotations, writer)
+    (cr.annotationMap.annotations.head) should be (check)
+  }
 }
 
 
 /**
- * An example test for testing module annotations
+ * Tests for Annotation Permissibility and Tenacity
+ *
+ * WARNING(izraelevitz): Not a complete suite of tests, requires the LowerTypes
+ * pass and ConstProp pass to correctly populate its RenameMap before Strict, Rigid, Firm,
+ * Unstable, Fickle, and Insistent can be tested.
  */
-class BrittleModuleAnnotationSpec extends AnnotationSpec with Matchers {
-   val compiler = new VerilogCompiler()
-   val input =
-"""
-circuit Top :
-  module Top :
-    input a : UInt<1>[2]
-    node x = a
-"""
-   val message = "This is Top"
-   val map: Map[Named, Annotation] = Map(ModuleName("Top") -> StringAnnotation(message))
-   val annotation = BrittleCircuitAnnotation(UnknownCAKind, map)
-   "The annotation" should "get passed through the compiler" in {
-      (getResult(annotation).annotations.head == annotation) should be (true)
-   }
+class AnnotationTests extends AnnotationSpec with Matchers {
+  def getAMap (a: Annotation): AnnotationMap = new AnnotationMap(Seq(a))
+  val tID = TransID(1)
+  val input =
+    """circuit Top :
+       |  module Top :
+       |    input a : UInt<1>[2]
+       |    input b : UInt<1>
+       |    node c = b""".stripMargin
+  val mName = ModuleName("Top", CircuitName("Top"))
+  val aName = ComponentName("a", mName)
+  val bName = ComponentName("b", mName)
+  val cName = ComponentName("c", mName)
+
+  "Loose and Sticky annotation on a node" should "pass through" in {
+    case class TestAnnotation(target: Named, tID: TransID) extends Annotation with Loose with Sticky {
+      def duplicate(to: Named) = this.copy(target=to)
+    }
+    val w = new StringWriter()
+    val ta = TestAnnotation(cName, tID)
+    execute(w, getAMap(ta), input, ta)
+  }
 }