All of src/ formatted with scalafmt

1 files changed, 177 insertions, 149 deletions

diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 4017503e..6f8dd574 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -15,7 +15,6 @@ import firrtl.util.BackendCompilationUtilities
 import firrtl.testutils._
 import org.scalatest.matchers.should.Matchers
 
-
 object AnnotationTests {
 
   class DeletingTransform extends Transform {
@@ -31,26 +30,26 @@ object AnnotationTests {
 abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with MakeCompiler {
   import AnnotationTests._
 
-  def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation
+  def anno(s:    String, value: String = "this is a value", mod: String = "Top"): Annotation
   def manno(mod: String): Annotation
 
   "Annotation on a node" should "pass through" in {
     val input: String =
       """circuit Top :
-         |  module Top :
-         |    input a : UInt<1>[2]
-         |    input b : UInt<1>
-         |    node c = b""".stripMargin
+        |  module Top :
+        |    input a : UInt<1>[2]
+        |    input b : UInt<1>
+        |    node c = b""".stripMargin
     val ta = anno("c", "")
     val r = compile(input, Seq(ta))
-    r.annotations.toSeq should contain (ta)
+    r.annotations.toSeq should contain(ta)
   }
 
   "Deleting annotations" should "create a DeletedAnnotation" in {
     val transform = Dependency[DeletingTransform]
     val compiler = makeVerilogCompiler(Seq(transform))
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input in: UInt<3>
         |""".stripMargin
@@ -65,7 +64,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
       result.getEmittedCircuit
     })
     val deleted = result.deletedAnnotations
-    exception.getMessage should be (s"No EmittedCircuit found! Did you delete any annotations?\n$deleted")
+    exception.getMessage should be(s"No EmittedCircuit found! Did you delete any annotations?\n$deleted")
   }
 
   "Renaming" should "propagate in Lowering of memories" in {
@@ -73,7 +72,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
     // Uncomment to help debugging failing tests
     // Logger.setClassLogLevels(Map(compiler.getClass.getName -> LogLevel.Debug))
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input in: UInt<3>
@@ -87,25 +86,24 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    m.r.en <= UInt(1)
         |    m.r.addr <= in
         |""".stripMargin
-    val annos = Seq(anno("m.r.data.b", "sub"), anno("m.r.data", "all"), anno("m", "mem"),
-                    dontTouch("Top.m"))
+    val annos = Seq(anno("m.r.data.b", "sub"), anno("m.r.data", "all"), anno("m", "mem"), dontTouch("Top.m"))
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("m_a", "mem"))
-    resultAnno should contain (anno("m_b_0", "mem"))
-    resultAnno should contain (anno("m_b_1", "mem"))
-    resultAnno should contain (anno("m_a.r.data", "all"))
-    resultAnno should contain (anno("m_b_0.r.data", "all"))
-    resultAnno should contain (anno("m_b_1.r.data", "all"))
-    resultAnno should contain (anno("m_b_0.r.data", "sub"))
-    resultAnno should contain (anno("m_b_1.r.data", "sub"))
+    resultAnno should contain(anno("m_a", "mem"))
+    resultAnno should contain(anno("m_b_0", "mem"))
+    resultAnno should contain(anno("m_b_1", "mem"))
+    resultAnno should contain(anno("m_a.r.data", "all"))
+    resultAnno should contain(anno("m_b_0.r.data", "all"))
+    resultAnno should contain(anno("m_b_1.r.data", "all"))
+    resultAnno should contain(anno("m_b_0.r.data", "sub"))
+    resultAnno should contain(anno("m_b_1.r.data", "sub"))
     resultAnno should not contain (anno("m"))
     resultAnno should not contain (anno("r"))
   }
   "Renaming" should "propagate in RemoveChirrtl and Lowering of memories" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input in: UInt<3>
@@ -115,14 +113,14 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
     val annos = Seq(anno("r.b", "sub"), anno("r", "all"), anno("m", "mem"), dontTouch("Top.m"))
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("m_a", "mem"))
-    resultAnno should contain (anno("m_b_0", "mem"))
-    resultAnno should contain (anno("m_b_1", "mem"))
-    resultAnno should contain (anno("m_a.r.data", "all"))
-    resultAnno should contain (anno("m_b_0.r.data", "all"))
-    resultAnno should contain (anno("m_b_1.r.data", "all"))
-    resultAnno should contain (anno("m_b_0.r.data", "sub"))
-    resultAnno should contain (anno("m_b_1.r.data", "sub"))
+    resultAnno should contain(anno("m_a", "mem"))
+    resultAnno should contain(anno("m_b_0", "mem"))
+    resultAnno should contain(anno("m_b_1", "mem"))
+    resultAnno should contain(anno("m_a.r.data", "all"))
+    resultAnno should contain(anno("m_b_0.r.data", "all"))
+    resultAnno should contain(anno("m_b_1.r.data", "all"))
+    resultAnno should contain(anno("m_b_0.r.data", "sub"))
+    resultAnno should contain(anno("m_b_1.r.data", "sub"))
     resultAnno should not contain (anno("m"))
     resultAnno should not contain (anno("r"))
   }
@@ -130,7 +128,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
   "Renaming" should "propagate in ZeroWidth" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input zero: UInt<0>
         |    wire x: {a: UInt<3>, b: UInt<0>}
@@ -141,11 +139,11 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    x.a <= zero
         |    x.b <= zero
         |""".stripMargin
-    val annos = Seq(anno("zero"), anno("x.a"), anno("x.b"), anno("y[0]"), anno("y[1]"),
-                    anno("y[2]"), dontTouch("Top.x"))
+    val annos =
+      Seq(anno("zero"), anno("x.a"), anno("x.b"), anno("y[0]"), anno("y[1]"), anno("y[2]"), dontTouch("Top.x"))
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("x_a"))
+    resultAnno should contain(anno("x_a"))
     resultAnno should not contain (anno("zero"))
     resultAnno should not contain (anno("x.a"))
     resultAnno should not contain (anno("x.b"))
@@ -161,7 +159,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
   "Renaming subcomponents" should "propagate in Lowering" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input pred: UInt<1>
@@ -176,12 +174,24 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    write <= in
         |""".stripMargin
     val annos = Seq(
-      anno("in.a"), anno("in.b[0]"), anno("in.b[1]"),
-      anno("out.a"), anno("out.b[0]"), anno("out.b[1]"),
-      anno("w.a"), anno("w.b[0]"), anno("w.b[1]"),
-      anno("r.a"), anno("r.b[0]"), anno("r.b[1]"),
-      anno("write.a"), anno("write.b[0]"), anno("write.b[1]"),
-      dontTouch("Top.r"), dontTouch("Top.w"), dontTouch("Top.mem")
+      anno("in.a"),
+      anno("in.b[0]"),
+      anno("in.b[1]"),
+      anno("out.a"),
+      anno("out.b[0]"),
+      anno("out.b[1]"),
+      anno("w.a"),
+      anno("w.b[0]"),
+      anno("w.b[1]"),
+      anno("r.a"),
+      anno("r.b[0]"),
+      anno("r.b[1]"),
+      anno("write.a"),
+      anno("write.b[0]"),
+      anno("write.b[1]"),
+      dontTouch("Top.r"),
+      dontTouch("Top.w"),
+      dontTouch("Top.mem")
     )
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
@@ -200,27 +210,27 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
     resultAnno should not contain (anno("r.a"))
     resultAnno should not contain (anno("r.b[0]"))
     resultAnno should not contain (anno("r.b[1]"))
-    resultAnno should contain (anno("in_a"))
-    resultAnno should contain (anno("in_b_0"))
-    resultAnno should contain (anno("in_b_1"))
-    resultAnno should contain (anno("out_a"))
-    resultAnno should contain (anno("out_b_0"))
-    resultAnno should contain (anno("out_b_1"))
-    resultAnno should contain (anno("w_a"))
-    resultAnno should contain (anno("w_b_0"))
-    resultAnno should contain (anno("w_b_1"))
-    resultAnno should contain (anno("r_a"))
-    resultAnno should contain (anno("r_b_0"))
-    resultAnno should contain (anno("r_b_1"))
-    resultAnno should contain (anno("mem_a.write.data"))
-    resultAnno should contain (anno("mem_b_0.write.data"))
-    resultAnno should contain (anno("mem_b_1.write.data"))
+    resultAnno should contain(anno("in_a"))
+    resultAnno should contain(anno("in_b_0"))
+    resultAnno should contain(anno("in_b_1"))
+    resultAnno should contain(anno("out_a"))
+    resultAnno should contain(anno("out_b_0"))
+    resultAnno should contain(anno("out_b_1"))
+    resultAnno should contain(anno("w_a"))
+    resultAnno should contain(anno("w_b_0"))
+    resultAnno should contain(anno("w_b_1"))
+    resultAnno should contain(anno("r_a"))
+    resultAnno should contain(anno("r_b_0"))
+    resultAnno should contain(anno("r_b_1"))
+    resultAnno should contain(anno("mem_a.write.data"))
+    resultAnno should contain(anno("mem_b_0.write.data"))
+    resultAnno should contain(anno("mem_b_1.write.data"))
   }
 
   "Renaming components" should "expand in Lowering" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input pred: UInt<1>
@@ -231,28 +241,27 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    out <= mux(pred, in, w)
         |    reg r: {a: UInt<3>, b: UInt<3>[2]}, clk
         |""".stripMargin
-    val annos = Seq(anno("in"), anno("out"), anno("w"), anno("r"), dontTouch("Top.r"),
-                    dontTouch("Top.w"))
+    val annos = Seq(anno("in"), anno("out"), anno("w"), anno("r"), dontTouch("Top.r"), dontTouch("Top.w"))
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("in_a"))
-    resultAnno should contain (anno("in_b_0"))
-    resultAnno should contain (anno("in_b_1"))
-    resultAnno should contain (anno("out_a"))
-    resultAnno should contain (anno("out_b_0"))
-    resultAnno should contain (anno("out_b_1"))
-    resultAnno should contain (anno("w_a"))
-    resultAnno should contain (anno("w_b_0"))
-    resultAnno should contain (anno("w_b_1"))
-    resultAnno should contain (anno("r_a"))
-    resultAnno should contain (anno("r_b_0"))
-    resultAnno should contain (anno("r_b_1"))
+    resultAnno should contain(anno("in_a"))
+    resultAnno should contain(anno("in_b_0"))
+    resultAnno should contain(anno("in_b_1"))
+    resultAnno should contain(anno("out_a"))
+    resultAnno should contain(anno("out_b_0"))
+    resultAnno should contain(anno("out_b_1"))
+    resultAnno should contain(anno("w_a"))
+    resultAnno should contain(anno("w_b_0"))
+    resultAnno should contain(anno("w_b_1"))
+    resultAnno should contain(anno("r_a"))
+    resultAnno should contain(anno("r_b_0"))
+    resultAnno should contain(anno("r_b_1"))
   }
 
   "Renaming subcomponents that aren't leaves" should "expand in Lowering" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input pred: UInt<1>
@@ -264,24 +273,23 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    out <= n
         |    reg r: {a: UInt<3>, b: UInt<3>[2]}, clk
         |""".stripMargin
-    val annos = Seq(anno("in.b"), anno("out.b"), anno("w.b"), anno("r.b"),
-                    dontTouch("Top.r"), dontTouch("Top.w"))
+    val annos = Seq(anno("in.b"), anno("out.b"), anno("w.b"), anno("r.b"), dontTouch("Top.r"), dontTouch("Top.w"))
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("in_b_0"))
-    resultAnno should contain (anno("in_b_1"))
-    resultAnno should contain (anno("out_b_0"))
-    resultAnno should contain (anno("out_b_1"))
-    resultAnno should contain (anno("w_b_0"))
-    resultAnno should contain (anno("w_b_1"))
-    resultAnno should contain (anno("r_b_0"))
-    resultAnno should contain (anno("r_b_1"))
+    resultAnno should contain(anno("in_b_0"))
+    resultAnno should contain(anno("in_b_1"))
+    resultAnno should contain(anno("out_b_0"))
+    resultAnno should contain(anno("out_b_1"))
+    resultAnno should contain(anno("w_b_0"))
+    resultAnno should contain(anno("w_b_1"))
+    resultAnno should contain(anno("r_b_0"))
+    resultAnno should contain(anno("r_b_1"))
   }
 
   "Renaming" should "track constprop + dce" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input clk: Clock
         |    input pred: UInt<1>
@@ -291,9 +299,15 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    out <= n
         |""".stripMargin
     val annos = Seq(
-      anno("in.a"), anno("in.b[0]"), anno("in.b[1]"),
-      anno("out.a"), anno("out.b[0]"), anno("out.b[1]"),
-      anno("n.a"), anno("n.b[0]"), anno("n.b[1]")
+      anno("in.a"),
+      anno("in.b[0]"),
+      anno("in.b[1]"),
+      anno("out.a"),
+      anno("out.b[0]"),
+      anno("out.b[1]"),
+      anno("n.a"),
+      anno("n.b[0]"),
+      anno("n.b[1]")
     )
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
@@ -309,18 +323,18 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
     resultAnno should not contain (anno("n_a"))
     resultAnno should not contain (anno("n_b_0"))
     resultAnno should not contain (anno("n_b_1"))
-    resultAnno should contain (anno("in_a"))
-    resultAnno should contain (anno("in_b_0"))
-    resultAnno should contain (anno("in_b_1"))
-    resultAnno should contain (anno("out_a"))
-    resultAnno should contain (anno("out_b_0"))
-    resultAnno should contain (anno("out_b_1"))
+    resultAnno should contain(anno("in_a"))
+    resultAnno should contain(anno("in_b_0"))
+    resultAnno should contain(anno("in_b_1"))
+    resultAnno should contain(anno("out_a"))
+    resultAnno should contain(anno("out_b_0"))
+    resultAnno should contain(anno("out_b_1"))
   }
 
   "Renaming" should "track deleted modules AND instances in dce" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Dead :
         |    input foo : UInt<8>
         |    output bar : UInt<8>
@@ -339,11 +353,17 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |""".stripMargin
     val annos = Seq(
       OptimizableExtModuleAnnotation(ModuleName("DeadExt", CircuitName("Top"))),
-      manno("Dead"), manno("DeadExt"), manno("Top"),
-      anno("d"), anno("d2"),
-      anno("foo", mod = "Top"), anno("bar", mod = "Top"),
-      anno("foo", mod = "Dead"), anno("bar", mod = "Dead"),
-      anno("foo", mod = "DeadExt"), anno("bar", mod = "DeadExt")
+      manno("Dead"),
+      manno("DeadExt"),
+      manno("Top"),
+      anno("d"),
+      anno("d2"),
+      anno("foo", mod = "Top"),
+      anno("bar", mod = "Top"),
+      anno("foo", mod = "Dead"),
+      anno("bar", mod = "Dead"),
+      anno("foo", mod = "DeadExt"),
+      anno("bar", mod = "DeadExt")
     )
     val result = compiler.transform(CircuitState(parse(input), annos))
     /* Uncomment to help debug
@@ -354,12 +374,12 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         case Annotation(target, _, _) => println(s"not deleted: $target")
       }
     }
-    */
+     */
     val resultAnno = result.annotations.toSeq
 
-    resultAnno should contain (manno("Top"))
-    resultAnno should contain (anno("foo", mod = "Top"))
-    resultAnno should contain (anno("bar", mod = "Top"))
+    resultAnno should contain(manno("Top"))
+    resultAnno should contain(anno("foo", mod = "Top"))
+    resultAnno should contain(anno("bar", mod = "Top"))
 
     resultAnno should not contain (manno("Dead"))
     resultAnno should not contain (manno("DeadExt"))
@@ -373,7 +393,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
 
   "Renaming" should "track deduplication" in {
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Child :
         |    input x : UInt<32>
         |    output y : UInt<32>
@@ -392,13 +412,16 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    out <= tail(add(a.y, b.y), 1)
         |""".stripMargin
     val annos = Seq(
-      anno("x", mod = "Child"), anno("y", mod = "Child_1"), manno("Child"), manno("Child_1")
+      anno("x", mod = "Child"),
+      anno("y", mod = "Child_1"),
+      manno("Child"),
+      manno("Child_1")
     )
     val result = compile(input, annos)
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("x", mod = "Child"))
-    resultAnno should contain (anno("y", mod = "Child"))
-    resultAnno should contain (manno("Child"))
+    resultAnno should contain(anno("x", mod = "Child"))
+    resultAnno should contain(anno("y", mod = "Child"))
+    resultAnno should contain(manno("Child"))
     resultAnno should not contain (anno("y", mod = "Child_1"))
     resultAnno should not contain (manno("Child_1"))
   }
@@ -412,7 +435,7 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
   "Annotations on empty aggregates" should "be deleted" in {
     val compiler = makeVerilogCompiler()
     val input =
-     """circuit Top :
+      """circuit Top :
         |  module Top :
         |    input x : { foo : UInt<8>, bar : {}, fizz : UInt<8>[0], buzz : UInt<0> }
         |    output y : { foo : UInt<8>, bar : {}, fizz : UInt<8>[0], buzz : UInt<0> }
@@ -423,12 +446,19 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
         |    y <= x
         |""".stripMargin
     val annos = Seq(
-      anno("x"), anno("y.bar"), anno("y.fizz"), anno("y.buzz"), anno("a"), anno("b"), anno("c"),
-      anno("c[0].d"), anno("c[1].d")
+      anno("x"),
+      anno("y.bar"),
+      anno("y.fizz"),
+      anno("y.buzz"),
+      anno("a"),
+      anno("b"),
+      anno("c"),
+      anno("c[0].d"),
+      anno("c[1].d")
     )
     val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
-    resultAnno should contain (anno("x_foo"))
+    resultAnno should contain(anno("x_foo"))
     resultAnno should not contain (anno("a"))
     resultAnno should not contain (anno("b"))
     // Check both with and without dots because both are wrong
@@ -445,8 +475,8 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
     resultAnno should not contain (anno("x_fizz"))
     resultAnno should not contain (anno("x_buzz"))
     resultAnno should not contain (anno("c"))
-    resultAnno should contain (anno("c_0_e"))
-    resultAnno should contain (anno("c_1_e"))
+    resultAnno should contain(anno("c_0_e"))
+    resultAnno should contain(anno("c_1_e"))
     resultAnno should not contain (anno("c[0].d"))
     resultAnno should not contain (anno("c[1].d"))
     resultAnno should not contain (anno("c_0_d"))
@@ -456,15 +486,14 @@ abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with
 
 class JsonAnnotationTests extends AnnotationTests {
   // Helper annotations
-  case class SimpleAnno(target: ComponentName, value: String) extends
-      SingleTargetAnnotation[ComponentName] {
+  case class SimpleAnno(target: ComponentName, value: String) extends SingleTargetAnnotation[ComponentName] {
     def duplicate(n: ComponentName) = this.copy(target = n)
   }
   case class ModuleAnno(target: ModuleName) extends SingleTargetAnnotation[ModuleName] {
     def duplicate(n: ModuleName) = this.copy(target = n)
   }
 
-  def anno(s: String, value: String ="this is a value", mod: String = "Top"): SimpleAnno =
+  def anno(s: String, value: String = "this is a value", mod: String = "Top"): SimpleAnno =
     SimpleAnno(ComponentName(s, ModuleName(mod, CircuitName("Top"))), value)
   def manno(mod: String): Annotation = ModuleAnno(ModuleName(mod, CircuitName("Top")))
 
@@ -487,17 +516,17 @@ class JsonAnnotationTests extends AnnotationTests {
 
     val readAnnos = JsonProtocol.deserializeTry(text).get
 
-    annos should be (readAnnos)
+    annos should be(readAnnos)
   }
 
   private def setupManager(annoFileText: Option[String]) = {
     val source = """
-      |circuit test :
-      |  module test :
-      |    input x : UInt<1>
-      |    output z : UInt<1>
-      |    z <= x
-      |    node y = x""".stripMargin
+                   |circuit test :
+                   |  module test :
+                   |    input x : UInt<1>
+                   |    output z : UInt<1>
+                   |    z <= x
+                   |    node y = x""".stripMargin
     val testDir = BackendCompilationUtilities.createTestDirectory(this.getClass.getSimpleName)
     val annoFile = new File(testDir, "anno.json")
 
@@ -519,58 +548,57 @@ class JsonAnnotationTests extends AnnotationTests {
   "Annotation file not found" should "give a reasonable error message" in {
     val manager = setupManager(None)
 
-    an [AnnotationFileNotFoundException] shouldBe thrownBy {
+    an[AnnotationFileNotFoundException] shouldBe thrownBy {
       Driver.execute(manager)
     }
   }
 
   "Annotation class not found" should "give a reasonable error message" in {
     val anno = """
-      |[
-      |  {
-      |    "class":"ThisClassDoesNotExist",
-      |    "target":"test.test.y"
-      |  }
-      |] """.stripMargin
+                 |[
+                 |  {
+                 |    "class":"ThisClassDoesNotExist",
+                 |    "target":"test.test.y"
+                 |  }
+                 |] """.stripMargin
     val manager = setupManager(Some(anno))
 
-    the [Exception] thrownBy Driver.execute(manager) should matchPattern {
+    the[Exception] thrownBy Driver.execute(manager) should matchPattern {
       case InvalidAnnotationFileException(_, _: AnnotationClassNotFoundException) =>
     }
   }
 
   "Malformed annotation file" should "give a reasonable error message" in {
     val anno = """
-      |[
-      |  {
-      |    "class":
-      |    "target":"test.test.y"
-      |  }
-      |] """.stripMargin
+                 |[
+                 |  {
+                 |    "class":
+                 |    "target":"test.test.y"
+                 |  }
+                 |] """.stripMargin
     val manager = setupManager(Some(anno))
 
-    the [Exception] thrownBy Driver.execute(manager) should matchPattern {
+    the[Exception] thrownBy Driver.execute(manager) should matchPattern {
       case InvalidAnnotationFileException(_, _: InvalidAnnotationJSONException) =>
     }
   }
 
   "Non-array annotation file" should "give a reasonable error message" in {
     val anno = """
-      |{
-      |  "class":"firrtl.transforms.DontTouchAnnotation",
-      |  "target":"test.test.y"
-      |}
-      |""".stripMargin
+                 |{
+                 |  "class":"firrtl.transforms.DontTouchAnnotation",
+                 |  "target":"test.test.y"
+                 |}
+                 |""".stripMargin
     val manager = setupManager(Some(anno))
 
-    the [Exception] thrownBy Driver.execute(manager) should matchPattern {
-      case InvalidAnnotationFileException(_, InvalidAnnotationJSONException(msg))
-        if msg.contains("JObject") =>
+    the[Exception] thrownBy Driver.execute(manager) should matchPattern {
+      case InvalidAnnotationFileException(_, InvalidAnnotationJSONException(msg)) if msg.contains("JObject") =>
     }
   }
 
   object DoNothingTransform extends Transform {
-    override def inputForm: CircuitForm = UnknownForm
+    override def inputForm:  CircuitForm = UnknownForm
     override def outputForm: CircuitForm = UnknownForm
 
     def execute(state: CircuitState): CircuitState = state
@@ -580,9 +608,9 @@ class JsonAnnotationTests extends AnnotationTests {
     val annos = Seq(anno("a"), anno("b"), anno("c"), anno("d"), anno("e"))
     val input: String =
       """circuit Top :
-         |  module Top :
-         |    input a : UInt<1>
-         |    node b = c""".stripMargin
+        |  module Top :
+        |    input a : UInt<1>
+        |    node b = c""".stripMargin
     val cr = DoNothingTransform.runTransform(CircuitState(parse(input), ChirrtlForm, annos))
     cr.annotations.toSeq shouldEqual annos
   }