Add RTLIL Backend. (#2331)

* Added RTLIL Backend.

* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.

* Fix build on scala 2.13

* Add additional equivalence test, make some bugfixes and perf opts to the emitter.

* Final changes as requested by Kevin, code cleanup, add support for formal cells.

2 files changed, 124 insertions, 0 deletions

diff --git a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilCompilationTest.scala b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilCompilationTest.scala
new file mode 100644
index 00000000..601271fc
--- /dev/null
+++ b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilCompilationTest.scala
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package firrtl.backends.experimental.rtlil.end2end
+
+import firrtl.stage.{FirrtlStage, OutputFileAnnotation}
+import firrtl.util.BackendCompilationUtilities
+import logger.LazyLogging
+import org.scalatest.flatspec.AnyFlatSpec
+
+import java.io.File
+import scala.sys.process.{Process, ProcessLogger}
+
+class RtlilCompilationTest extends AnyFlatSpec with LazyLogging {
+  it should "generate valid RTLIL for AddNot" in { compileAndParse("AddNot") }
+  it should "generate valid RTLIL for FPU" in { compileAndParse("FPU") }
+  it should "generate valid RTLIL for HwachaSequencer" in { compileAndParse("HwachaSequencer") }
+  it should "generate valid RTLIL for ICache" in { compileAndParse("ICache") }
+  it should "generate valid RTLIL for Ops" in { compileAndParse("Ops") }
+  it should "generate valid RTLIL for Rob" in { compileAndParse("Rob") }
+  it should "generate valid RTLIL for RocketCore" in { compileAndParse("RocketCore") }
+
+  private def compileAndParse(name: String): Unit = {
+    val testDir = BackendCompilationUtilities.createTestDirectory(name + "-rtlil")
+    val inputFile = new File(testDir, s"${name}.fir")
+    BackendCompilationUtilities.copyResourceToFile(s"/regress/${name}.fir", inputFile)
+
+    val args = Array(
+      "-ll",
+      "error", // surpress warnings to keep test output clean
+      "--target-dir",
+      testDir.toString,
+      "-i",
+      inputFile.toString,
+      "-E",
+      "experimental-rtlil",
+      "-E",
+      "verilog",
+      "-E",
+      "low"
+    )
+    val res = (new FirrtlStage).execute(args, Seq())
+    val fileName = res.collectFirst { case OutputFileAnnotation(file) => file }.get
+
+    val rtlilFile = testDir.toString + "/" + fileName + ".il"
+    val log = ProcessLogger(_ => (), logger.error(_))
+    //memory_collect is here to verify that the emitted $mem(wr|rd) cells are proper.
+    val yosysRet = Process(Seq("yosys", "-p", s"read_rtlil ${rtlilFile}; memory_collect")).run(log).exitValue()
+    assert(yosysRet == 0, s"Failed to parse RTLIL file $rtlilFile generated for $name")
+  }
+}
diff --git a/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala
new file mode 100644
index 00000000..7475d6cb
--- /dev/null
+++ b/src/test/scala/firrtl/backends/experimental/rtlil/end2end/RtlilEquivalenceTest.scala
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package firrtl.backends.experimental.rtlil.end2end
+
+import firrtl.stage.{FirrtlStage, OutputFileAnnotation}
+import firrtl.util.BackendCompilationUtilities
+import logger.LazyLogging
+import org.scalatest.flatspec.AnyFlatSpec
+
+import java.io.File
+import scala.sys.process.{Process, ProcessLogger}
+
+class RtlilEquivalenceTest extends AnyFlatSpec with LazyLogging {
+  it should "generate identical RTLIL for Can_Core" in { compileAndParse("CanTop") }
+  it should "generate identical RTLIL for RotationCordic" in { compileAndParse("RotationCordic") }
+
+  private def compileAndParse(name: String): Unit = {
+    val testDir = BackendCompilationUtilities.createTestDirectory(name + "-rtlil")
+    val inputFile = new File(testDir, s"${name}.fir")
+    BackendCompilationUtilities.copyResourceToFile(s"/rtlil_equiv_check/${name}.fir", inputFile)
+
+    val args = Array(
+      "-ll",
+      "error",
+      "--target-dir",
+      testDir.toString,
+      "-i",
+      inputFile.toString,
+      "-E",
+      "experimental-rtlil",
+      "-E",
+      "low",
+      "-E",
+      "verilog"
+    )
+    val res = (new FirrtlStage).execute(args, Seq())
+    val fileName = res.collectFirst { case OutputFileAnnotation(file) => file }.get
+
+    val rtlilFile = testDir.toString + "/" + fileName + ".il"
+    val verilogFile = testDir.toString + "/" + fileName + ".v"
+
+    val log = ProcessLogger(
+      msg => {
+        println(msg)
+      },
+      logger.error(_)
+    )
+
+    val yosysArgs = Array(
+      s"read_rtlil ${rtlilFile};",
+      s"prep -flatten -top ${name};",
+      "design -stash gate;",
+      s"read_verilog ${verilogFile};",
+      s"prep -flatten -top ${name};",
+      "design -stash gold;",
+      s"design -copy-from gold -as gold ${name};",
+      s"design -copy-from gate -as gate ${name};",
+      "select gold gate;",
+      "opt -full -fine;",
+      "memory;",
+      "async2sync;",
+      "equiv_make gold gate equiv;",
+      "select equiv;",
+      "equiv_struct;",
+      "equiv_simple -seq 1;",
+      "equiv_status;",
+      "equiv_induct -seq 1 -undef;",
+      "equiv_status -assert"
+    )
+    println(yosysArgs.mkString(" "))
+    val yosysRet = Process(Seq("yosys", "-p", yosysArgs.mkString(" "))).run(log).exitValue()
+    assert(yosysRet == 0, s"Unable to prove equivalence of design ${name}.")
+  }
+}