Improve performance of LowerTypes renaming (#2024)

This is done by having LowerTypes uses two RenameMaps instead of one for
each module. There is one for renaming instance paths, and one for
renaming everything within modules.

Also add some utilities:
* TargetUtils for dealing with InstanceTargets
* RenameMap.fromInstanceRenames

2 files changed, 63 insertions, 8 deletions

diff --git a/src/test/scala/firrtl/RenameMapPrivateSpec.scala b/src/test/scala/firrtl/RenameMapPrivateSpec.scala
new file mode 100644
index 00000000..d735e6c8
--- /dev/null
+++ b/src/test/scala/firrtl/RenameMapPrivateSpec.scala
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package firrtl
+
+import firrtl.annotations.Target
+import firrtl.annotations.TargetToken.{Instance, OfModule}
+import firrtl.analyses.InstanceKeyGraph
+import firrtl.testutils.FirrtlFlatSpec
+
+class RenameMapPrivateSpec extends FirrtlFlatSpec {
+  "RenameMap.fromInstanceRenames" should "handle instance renames" in {
+    def tar(str: String): Target = Target.deserialize(str)
+    val circuit = parse(
+      """circuit Top :
+        |  module Bar :
+        |    skip
+        |  module Foo :
+        |    inst bar of Bar
+        |  module Top :
+        |    inst foo1 of Foo
+        |    inst foo2 of Foo
+        |    inst bar of Bar
+        |""".stripMargin
+    )
+    val graph = InstanceKeyGraph(circuit)
+    val renames = Map(
+      OfModule("Foo") -> Map(Instance("bar") -> Instance("bbb")),
+      OfModule("Top") -> Map(Instance("foo1") -> Instance("ffff"))
+    )
+    val rm = RenameMap.fromInstanceRenames(graph, renames)
+    rm.get(tar("~Top|Top/foo1:Foo")) should be(Some(Seq(tar("~Top|Top/ffff:Foo"))))
+    rm.get(tar("~Top|Top/foo2:Foo")) should be(None)
+    // Check of nesting
+    rm.get(tar("~Top|Top/foo1:Foo/bar:Bar")) should be(Some(Seq(tar("~Top|Top/ffff:Foo/bbb:Bar"))))
+    rm.get(tar("~Top|Top/foo2:Foo/bar:Bar")) should be(Some(Seq(tar("~Top|Top/foo2:Foo/bbb:Bar"))))
+    rm.get(tar("~Top|Foo/bar:Bar")) should be(Some(Seq(tar("~Top|Foo/bbb:Bar"))))
+    rm.get(tar("~Top|Top/bar:Bar")) should be(None)
+  }
+}
diff --git a/src/test/scala/firrtl/passes/LowerTypesSpec.scala b/src/test/scala/firrtl/passes/LowerTypesSpec.scala
index 70fa51fd..7ca98544 100644
--- a/src/test/scala/firrtl/passes/LowerTypesSpec.scala
+++ b/src/test/scala/firrtl/passes/LowerTypesSpec.scala
@@ -2,10 +2,13 @@
 
 package firrtl.passes
 import firrtl.annotations.{CircuitTarget, IsMember}
+import firrtl.annotations.TargetToken.{Instance, OfModule}
+import firrtl.analyses.InstanceKeyGraph
 import firrtl.{CircuitState, RenameMap, Utils}
 import firrtl.options.Dependency
 import firrtl.stage.TransformManager
 import firrtl.stage.TransformManager.TransformDependency
+import firrtl.testutils.FirrtlMatchers
 import org.scalatest.flatspec.AnyFlatSpec
 
 /** Unit test style tests for [[LowerTypes]].
@@ -228,22 +231,35 @@ class LowerTypesRenamingSpec extends AnyFlatSpec {
 }
 
 /** Instances are a special case since they do not get completely destructed but instead become a 1-deep bundle. */
-class LowerTypesOfInstancesSpec extends AnyFlatSpec {
+class LowerTypesOfInstancesSpec extends AnyFlatSpec with FirrtlMatchers {
   import LowerTypesSpecUtils._
   private case class Lower(inst: firrtl.ir.DefInstance, fields: Seq[String], renameMap: RenameMap)
   private val m = CircuitTarget("m").module("m")
+  private val igraph = InstanceKeyGraph(
+    parse(
+      """circuit m:
+        |  module c:
+        |    skip
+        |  module m:
+        |    inst i of c
+        |""".stripMargin
+    )
+  )
   def resultToFieldSeq(res: Seq[(String, firrtl.ir.SubField)]): Seq[String] =
     res.map(_._2).map(r => s"${r.name} : ${r.tpe.serialize}")
   private def lower(
-    n:         String,
-    tpe:       String,
-    module:    String,
-    namespace: Set[String],
-    renames:   RenameMap = RenameMap()
+    n:            String,
+    tpe:          String,
+    module:       String,
+    namespace:    Set[String],
+    otherRenames: RenameMap = RenameMap()
   ): Lower = {
     val ref = firrtl.ir.DefInstance(firrtl.ir.NoInfo, n, module, parseType(tpe))
     val mutableSet = scala.collection.mutable.HashSet[String]() ++ namespace
-    val (newInstance, res) = DestructTypes.destructInstance(m, ref, mutableSet, renames, Set())
+    val instRenames = scala.collection.mutable.ListBuffer[(Instance, Instance)]()
+    val (newInstance, res) = DestructTypes.destructInstance(m, ref, mutableSet, instRenames, Set())
+    val instMap = Map(OfModule("m") -> instRenames.toMap)
+    val renames = RenameMap.fromInstanceRenames(igraph, instMap).andThen(otherRenames)
     Lower(newInstance, resultToFieldSeq(res), renames)
   }
   private def get(l: Lower, m: IsMember): Set[IsMember] = l.renameMap.get(m).get.toSet
@@ -305,7 +321,7 @@ class LowerTypesOfInstancesSpec extends AnyFlatSpec {
       assert(get(l, i) == Set(i_))
 
       // the ports renaming is also noted
-      val r = portRenames.andThen(otherRenames)
+      val r = portRenames.andThen(l.renameMap)
       assert(r.get(i.ref("b")).get == Seq(i_.ref("b__c")))
       assert(r.get(i.ref("b").field("c")).get == Seq(i_.ref("b__c")))
       assert(r.get(i.ref("b_c")).get == Seq(i_.ref("b_c")))