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authorKevin Laeufer2022-12-15 17:09:14 -0500
committerGitHub2022-12-15 14:09:14 -0800
commit135739f0c7ef3f6404ba7115f77c7d7b913f6748 (patch)
tree5de3fb957eff020a10bd665ae411f63b8e2675ed /src/test/scala/firrtl
parent64ac2d2cb866f5c3e30544bb1087dd374b57fdcb (diff)
0-bit literals (#2544)
* allow for zero-width integer literals * CheckWidths: ensure that width is non-negative
Diffstat (limited to 'src/test/scala/firrtl')
-rw-r--r--src/test/scala/firrtl/testutils/LeanTransformSpec.scala4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/test/scala/firrtl/testutils/LeanTransformSpec.scala b/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
index d3510326..2d1cad8d 100644
--- a/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
+++ b/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
@@ -35,6 +35,10 @@ class LeanTransformSpec(protected val transforms: Seq[TransformDependency])
actual should be(expected)
finalState
}
+ protected def removeSkip(c: ir.Circuit): ir.Circuit = {
+ def onStmt(s: ir.Statement): ir.Statement = s.mapStmt(onStmt)
+ c.mapModule(m => m.mapStmt(onStmt))
+ }
}
private object LeanTransformSpec {