Fix equivalence tests (#853)

* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter
- add RemoveValidIf pass to MinimumLowFirrtlOptimization

* add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract

* change types of inputForm/outputForm to CircuitForm

* change EquivalenceTest message

* remove ICache equivalence tests

* fix rebase errors

* Add Ops scalatests to LEC suite

* Only run compiler-path-comparison LEC tests on Ops design

* Fixup issues with merge

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>

1 files changed, 18 insertions, 3 deletions

diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
index 8f0241fe..c9cd1ecd 100644
--- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
@@ -77,12 +77,12 @@ trait FirrtlRunners extends BackendCompilationUtilities {
     * @param input string containing Firrtl source
     * @param customTransforms Firrtl transforms to test for equivalence
     * @param customAnnotations Optional Firrtl annotations
-    * @param resets tell yosys which signals to set for SAT, format is (timestep, signal, value)
+    * @param timesteps the maximum number of timesteps to consider
     */
   def firrtlEquivalenceTest(input: String,
                             customTransforms: Seq[Transform] = Seq.empty,
                             customAnnotations: AnnotationSeq = Seq.empty,
-                            resets: Seq[(Int, String, Int)] = Seq.empty): Unit = {
+                            timesteps: Int = 1): Unit = {
     val circuit = Parser.parse(input.split("\n").toIterator)
     val prefix = circuit.main
     val testDir = createTestDirectory(prefix + "_equivalence_test")
@@ -112,7 +112,7 @@ trait FirrtlRunners extends BackendCompilationUtilities {
     val refResult = (new firrtl.stage.FirrtlStage).run(refAnnos)
     val refName = refResult.collectFirst({ case stage.FirrtlCircuitAnnotation(c) => c.main }).getOrElse(refSuggestedName)
 
-    assert(yosysExpectSuccess(customName, refName, testDir, resets))
+    assert(BackendCompilationUtilities.yosysExpectSuccess(customName, refName, testDir, timesteps))
   }
 
   /** Compiles input Firrtl to Verilog */
@@ -430,5 +430,20 @@ trait Utils {
       System.setSecurityManager(null)
     }
   }
+}
+
+/** Super class for equivalence driven Firrtl tests */
+abstract class EquivalenceTest(transforms: Seq[Transform], name: String, dir: String) extends FirrtlFlatSpec {
+  val fileName = s"$dir/$name.fir"
+  val in = getClass.getResourceAsStream(fileName)
+  if (in == null) {
+    throw new FileNotFoundException(s"Resource '$fileName'")
+  }
+  val source = scala.io.Source.fromInputStream(in)
+  val input = try source.mkString finally source.close()
 
+  s"$name with ${transforms.map(_.name).mkString(", ")}" should
+    s"be equivalent to $name without ${transforms.map(_.name).mkString(", ")}" in {
+    firrtlEquivalenceTest(input, transforms)
+  }
 }