Allow Side Effecting Statement to have Names (#2057)

* firrtl: add optional statement labels for stop, printf, assert, assume and cover

* test: parsing of statement labels

* ir: ensure that name is properly retained

* SymbolTable: add support for labled statements

* test: parsing statement labels

* test: lower types name collisions with named statements

* ignore empty names

* Inline: deal with named and unnamed statements

* RemoveWires: treat stop, printf and verification statements as "others"

* test: fix InlineInstance tests

* DeadCodeEliminations: statements are now als declarations

* CheckHighForm: ensure that statement names are not used as references

* CheckSpec: throw error if statement name collides

* add pass to automatically add missing statement names

* check: make sure that two statements cannot have the same name

* stmtLabel -> stmtName

* scalafmt

* add statement names to spec

* spec: meta data -> metadata

* EnsureStatementNames: explain naming algorithm

* remove returns

* better namespace use

* ir: add CanBeReferenced trait

* ir: add newline as jack requested

1 files changed, 5 insertions, 6 deletions

diff --git a/src/test/scala/firrtl/testutils/FirrtlSpec.scala b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
index 6de2af1e..24793437 100644
--- a/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+++ b/src/test/scala/firrtl/testutils/FirrtlSpec.scala
@@ -123,21 +123,21 @@ trait FirrtlRunners extends BackendCompilationUtilities {
   }
 
   /** Check equivalence of Firrtl with reference Verilog
-   *
+    *
     * @note the name of the reference Verilog module is grabbed via regex
     * @param inputFirrtl string containing Firrtl source
     * @param referenceVerilog Verilog that will be used as reference for LEC
     * @param timesteps the maximum number of timesteps to consider
     */
   def firrtlEquivalenceWithVerilog(
-    inputFirrtl:       String,
-    referenceVerilog:  String,
-    timesteps:         Int = 1
+    inputFirrtl:      String,
+    referenceVerilog: String,
+    timesteps:        Int = 1
   ): Unit = {
     val VerilogModule = """(?s).*module\s(\w+).*""".r
     val refName = referenceVerilog match {
       case VerilogModule(name) => name
-      case _ => throw new Exception(s"Reference Verilog must match simple regex! $VerilogModule")
+      case _                   => throw new Exception(s"Reference Verilog must match simple regex! $VerilogModule")
     }
     val circuit = Parser.parse(inputFirrtl.split("\n").toIterator)
     val inputName = circuit.main
@@ -163,7 +163,6 @@ trait FirrtlRunners extends BackendCompilationUtilities {
     assert(BackendCompilationUtilities.yosysExpectSuccess(inputName, refName, testDir, timesteps))
   }
 
-
   /** Compiles input Firrtl to Verilog */
   def compileToVerilog(input: String, annotations: AnnotationSeq = Seq.empty): String = {
     val circuit = Parser.parse(input.split("\n").toIterator)