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authorgrebe2017-01-19 09:12:13 -0800
committerAdam Izraelevitz2017-01-19 09:12:13 -0800
commitb0623fe1856caeba11cda1ccaf68f094489169a7 (patch)
tree38b1c247c9a3a51ca0a824eac1248933df2a2a69 /src/test/resources/top.cpp
parent8a1cdf15d131e086ddc9de6bfe8cd90ed7fb3eb7 (diff)
Verilog rem fix (#404)
* Add pass that fixes up widths with modulus operator for verilog * Add basic test for Verilog emission of Rem * Oops, left in some printlns.
Diffstat (limited to 'src/test/resources/top.cpp')
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