Refactor Compilers and Transforms

* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter

1 files changed, 33 insertions, 0 deletions

diff --git a/src/test/resources/features/CustomTransform.fir b/src/test/resources/features/CustomTransform.fir
new file mode 100644
index 00000000..941a9e9c
--- /dev/null
+++ b/src/test/resources/features/CustomTransform.fir
@@ -0,0 +1,33 @@
+circuit CustomTransform :
+  ; Replaced in custom transform by an implementation
+  extmodule Delay :
+    input clk : Clock
+    input reset : UInt<1>
+    input a : UInt<32>
+    input en : UInt<1>
+    output b : UInt<32>
+
+  module CustomTransform :
+    input clk : Clock
+    input reset : UInt<1>
+
+    reg cycle : UInt<32>, clk with : (reset => (reset, UInt<32>(0)))
+    cycle <= tail(add(cycle, UInt<32>(1)), 1)
+
+    inst delay of Delay
+    delay.clk <= clk
+    delay.reset <= reset
+    delay.a <= UInt(0)
+    delay.en <= UInt(0)
+
+    when eq(cycle, UInt(0)) :
+      delay.en <= UInt(1)
+      delay.a <= UInt("hdeadbeef")
+    when eq(cycle, UInt(1)) :
+      when neq(delay.b, UInt("hdeadbeef")) :
+        printf(clk, UInt(1), "Assertion failed!\n")
+        stop(clk, UInt(1), 1)
+    when eq(cycle, UInt(2)) :
+      printf(clk, UInt(1), "Success!\n")
+      stop(clk, UInt(1), 0)
+