Don't include verilog header files in "FileList" for VCS/Verilator. (#918)

When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917

2 files changed, 13 insertions, 0 deletions

diff --git a/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v
new file mode 100644
index 00000000..fcba38d5
--- /dev/null
+++ b/src/test/resources/blackboxes/ParameterizedViaHeaderAdderExtModule.v
@@ -0,0 +1,8 @@
+// See LICENSE for license details.
+module ParameterizedViaHeaderAdderExtModule(
+  input [15:0] foo,
+  output [15:0] bar
+);
+  `include "VerilogHeaderFile.vh"
+  assign bar = foo + VALUE;
+endmodule
diff --git a/src/test/resources/blackboxes/VerilogHeaderFile.vh b/src/test/resources/blackboxes/VerilogHeaderFile.vh
new file mode 100644
index 00000000..0844c95f
--- /dev/null
+++ b/src/test/resources/blackboxes/VerilogHeaderFile.vh
@@ -0,0 +1,5 @@
+// See LICENSE for license details.
+`ifndef _parameters_vh_
+`define _parameters_vh_
+parameter VALUE = 2;
+`endif