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authorJack Koenig2017-02-26 18:34:30 -0800
committerGitHub2017-02-26 18:34:30 -0800
commit6b030c982c11a330c81daeee7b798f6c147b9a05 (patch)
tree565a8b2fdceab1904dcdede7e3cfa1f5ca4b1d6f /src/test/resources/blackboxes/RenamedExtModuleTester.fir
parent1f9fd2f9b9e9a0117b0dd65524c9dcb767c02778 (diff)
Align types and names of ports in emitted Verilog (#463)
Diffstat (limited to 'src/test/resources/blackboxes/RenamedExtModuleTester.fir')
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