Add Support for Parameterized ExtModules and Name Override

Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.

1 files changed, 22 insertions, 0 deletions

diff --git a/src/test/resources/blackboxes/RenamedExtModuleTester.fir b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
new file mode 100644
index 00000000..48b0886c
--- /dev/null
+++ b/src/test/resources/blackboxes/RenamedExtModuleTester.fir
@@ -0,0 +1,22 @@
+circuit RenamedExtModuleTester :
+  extmodule ThisIsJustTheFirrtlName :
+    input foo : UInt<16>
+    output bar : UInt<16>
+
+    defname = SimpleExtModule
+
+  module RenamedExtModuleTester :
+    input clk : Clock
+    input reset : UInt<1>
+
+    inst dut of ThisIsJustTheFirrtlName
+
+    dut.foo <= UInt(1234)
+
+    when not(reset) :
+      when neq(dut.bar, UInt(1234)) :
+        printf(clk, not(reset), "Assertion failed\nTest Failed!\n")
+        stop(clk, not(reset), 1)
+      else :
+        stop(clk, not(reset), 0)
+