diff options
| author | David Biancolin | 2019-01-22 18:02:19 -0500 |
|---|---|---|
| committer | GitHub | 2019-01-22 18:02:19 -0500 |
| commit | df3c3fb5eedd3e2ac95b9f210268e4e515d6344c (patch) | |
| tree | 8423d9d1b496de8d380d0d0d5fda8a8a6564fa09 /src/main | |
| parent | 1d566b66bfd1b8809b2b605552343dc665dfd3c9 (diff) | |
| parent | bbd6eafe8943dc5dc2d44e5e67ac4c9dd96594bb (diff) | |
Merge pull request #969 from freechipsproject/top-wiring-aggregates
[Top Wiring] Expand top wiring to work on aggregates
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 80572b30..4a6d17d4 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -36,8 +36,8 @@ case class TopWiringAnnotation(target: ComponentName, prefix: String) extends * @note This *does* work for deduped modules */ class TopWiringTransform extends Transform { - def inputForm: CircuitForm = LowForm - def outputForm: CircuitForm = LowForm + def inputForm: CircuitForm = MidForm + def outputForm: CircuitForm = MidForm type InstPath = Seq[String] |