Merge pull request #1932 from freechipsproject/fix_VerilogPrep

Fix verilog prep

2 files changed, 1 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala
index 1dbc46ad..7be876ef 100644
--- a/src/main/scala/firrtl/transforms/ManipulateNames.scala
+++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala
@@ -185,7 +185,7 @@ abstract class ManipulateNames[A <: ManipulateNames[_]: ClassTag] extends Transf
   override def optionalPrerequisites:  Seq[TransformDependency] = Seq.empty
   override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
   override def invalidates(a: Transform) = a match {
-    case _: analyses.GetNamespace => true
+    case passes.InferTypes | _: analyses.GetNamespace => true
     case _ => false
   }
 
diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 3cf0e40a..0bf6419f 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -47,6 +47,4 @@ class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
 
   override def optionalPrerequisiteOf = Seq.empty
 
-  override def invalidates(a: Transform) = false
-
 }