Keep package name + directory structure consistent (#354)

* Keep package name + directory structure consistent

This annoyed me so heres a PR

* fix InferReadWrite references

* delete .ConvertFixedToSInt.scala.swo

5 files changed, 7 insertions, 5 deletions

diff --git a/src/main/scala/firrtl/ExecutionOptionsManager.scala b/src/main/scala/firrtl/ExecutionOptionsManager.scala
index ff725e30..e4954610 100644
--- a/src/main/scala/firrtl/ExecutionOptionsManager.scala
+++ b/src/main/scala/firrtl/ExecutionOptionsManager.scala
@@ -4,7 +4,7 @@ package firrtl
 
 import firrtl.Annotations._
 import firrtl.Parser._
-import firrtl.passes.memlib.ReplSeqMemAnnotation
+import firrtl.passes.memlib.{InferReadWriteAnnotation, ReplSeqMemAnnotation}
 import logger.LogLevel
 import scopt.OptionParser
 
@@ -267,7 +267,7 @@ trait HasFirrtlOptions {
     .valueName ("<circuit>")
     .foreach { x =>
       firrtlOptions = firrtlOptions.copy(
-        annotations = firrtlOptions.annotations :+ passes.InferReadWriteAnnotation(x, TransID(-1))
+        annotations = firrtlOptions.annotations :+ InferReadWriteAnnotation(x, TransID(-1))
       )
     }.text {
       "Enable readwrite port inference for the target circuit"
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 33553179..f42d11ba 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -146,7 +146,7 @@ class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with Simple
     passes.ConstProp,
     passes.Legalize,
     passes.VerilogWrap,
-    passes.VerilogMemDelays,
+    passes.memlib.VerilogMemDelays,
     passes.ConstProp,
     passes.SplitExpressions,
     passes.CommonSubexpressionElimination,
@@ -191,7 +191,7 @@ class LowFirrtlCompiler extends Compiler {
     new passes.InlineInstances(TransID(0)),
     new ResolveAndCheck,
     new HighFirrtlToMiddleFirrtl,
-    new passes.InferReadWrite(TransID(-1)),
+    new passes.memlib.InferReadWrite(TransID(-1)),
     new passes.memlib.ReplSeqMem(TransID(-2)),
     new MiddleFirrtlToLowFirrtl,
     new EmitFirrtl(writer)
@@ -205,7 +205,7 @@ class VerilogCompiler extends Compiler {
     new IRToWorkingIR,
     new ResolveAndCheck,
     new HighFirrtlToMiddleFirrtl,
-    new passes.InferReadWrite(TransID(-1)),
+    new passes.memlib.InferReadWrite(TransID(-1)),
     new passes.memlib.ReplSeqMem(TransID(-2)),
     new MiddleFirrtlToLowFirrtl,
     new passes.InlineInstances(TransID(0)),
diff --git a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo b/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo
deleted file mode 100644
index abd7c349..00000000
--- a/src/main/scala/firrtl/passes/.ConvertFixedToSInt.scala.swo
+++ /dev/null
diff --git a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
index ffdea1f2..28291135 100644
--- a/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
+++ b/src/main/scala/firrtl/passes/memlib/InferReadWrite.scala
@@ -26,6 +26,7 @@ MODIFICATIONS.
 */
 
 package firrtl.passes
+package memlib
 
 import firrtl._
 import firrtl.ir._
diff --git a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
index 2f7126b4..3aa63942 100644
--- a/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala
@@ -26,6 +26,7 @@ MODIFICATIONS.
 */
 
 package firrtl.passes
+package memlib
 
 import firrtl._
 import firrtl.ir._