diff options
| author | Albert Magyar | 2020-09-04 13:00:14 -0700 |
|---|---|---|
| committer | GitHub | 2020-09-04 13:00:14 -0700 |
| commit | b25c90f27bcf5ff61d7f0d16fb274759a628a500 (patch) | |
| tree | a5f0d18c40a33151f4eaddec86307532929f90c7 /src/main | |
| parent | 3b12706287bfbb07cff09a101aab1abedb522858 (diff) | |
| parent | 8dbecda01a4d9b400f89cb5c858352d763365f51 (diff) | |
Merge pull request #1883 from freechipsproject/legalize-mem-clocks
Legalize mem port clocks to avoid Verilator-unfriendly sensitivity lists
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala b/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala index 5a1ccdbf..0edf0cc6 100644 --- a/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala +++ b/src/main/scala/firrtl/transforms/LegalizeClocksAndAsyncResets.scala @@ -52,6 +52,9 @@ object LegalizeClocksAndAsyncResetsTransform { (None, rxClock) } Block(clockNodeOpt ++: resetNodeOpt ++: Seq(rx)) + case Connect(info, loc, rhs @ DoPrim(_, _, _, ClockType)) if (Utils.kind(loc) == MemKind) => + val node = DefNode(info, namespace.newTemp, rhs) + Block(node, Connect(info, loc, WRef(node))) case p: Print if isLiteralExpression(p.clk) => val node = DefNode(p.info, namespace.newTemp, p.clk) val px = p.copy(clk = WRef(node)) |