diff options
| author | Schuyler Eldridge | 2019-10-09 20:07:26 -0400 |
|---|---|---|
| committer | GitHub | 2019-10-09 20:07:26 -0400 |
| commit | 973ecf516c0ef2b222f2eb68dc8b514767db59af (patch) | |
| tree | 8788b25bafa0d4198d3af077070a4616aac09ecb /src/main | |
| parent | 357eba4c2b1549de70843899b4dae7d657757d50 (diff) | |
| parent | 75fd8d3eec98adb2f777e609ae1beea57ee5eedd (diff) | |
Merge pull request #1199 from freechipsproject/top-wiring-idempotent
Make TopWiringTransform Idempotent
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 65281382..fb6f73b4 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -261,7 +261,13 @@ class TopWiringTransform extends Transform { val newCircuit = state.circuit.copy(modules = modulesx) val fixedCircuit = fixupCircuit(newCircuit) val mappings = sources(state.circuit.main).zipWithIndex - (state.copy(circuit = fixedCircuit), mappings) + + val annosx = state.annotations.filter { + case _: TopWiringAnnotation => false + case _ => true + } + + (state.copy(circuit = fixedCircuit, annotations = annosx), mappings) } else { (state, List.empty) } //Generate output files based on the mapping. |
