Don't include verilog header files in "FileList" for VCS/Verilator. (#918)

When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917

1 files changed, 3 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
index 31c2a04b..61045c00 100644
--- a/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
+++ b/src/main/scala/firrtl/transforms/BlackBoxSourceHelper.scala
@@ -106,7 +106,9 @@ class BlackBoxSourceHelper extends firrtl.Transform {
       file
     }
 
-    BlackBoxSourceHelper.writeFileList(resourceFiles ++ inlineFiles, targetDir)
+    // Issue #917 - We don't want to list Verilog header files ("*.vh") in our file list - they will automatically be included by reference.
+    val verilogSourcesOnly = (resourceFiles ++ inlineFiles).filterNot( _.getName().endsWith(".vh"))
+    BlackBoxSourceHelper.writeFileList(verilogSourcesOnly, targetDir)
 
     state
   }