diff options
| author | Colin Schmidt | 2016-04-19 09:51:24 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-24 10:42:18 -0700 |
| commit | 243ff24f8eb9aae18bb0c7afe4f4c1e6cd66c084 (patch) | |
| tree | 7b35106bb2b01747538b664fbb78bf8d87967039 /src/main | |
| parent | 89cbd83265c5bfb3968865ebaddf79efb4f47050 (diff) | |
add better type mismatch error message
also check for it int unittest
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 618c0e99..b68b7431 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -306,7 +306,7 @@ object CheckTypes extends Pass with LazyLogging { class AccessIndexNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Access index must be a UInt type.") class IndexNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Index is not of UIntType.") class EnableNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}] Enable is not of UIntType.") - class InvalidConnect(info:Info) extends PassException(s"${info}: [module ${mname}] Type mismatch.") + class InvalidConnect(info:Info, lhs:String, rhs:String) extends PassException(s"${info}: [module ${mname}] Type mismatch. Cannot connect ${lhs} to ${rhs}.") class InvalidRegInit(info:Info) extends PassException(s"${info}: [module ${mname}] Type of init must match type of DefRegister.") class PrintfArgNotGround(info:Info) extends PassException(s"${info}: [module ${mname}] Printf arguments must be either UIntType or SIntType.") class ReqClk(info:Info) extends PassException(s"${info}: [module ${mname}] Requires a clock typed signal.") @@ -479,9 +479,9 @@ object CheckTypes extends Pass with LazyLogging { def check_types_s (s:Stmt) : Stmt = { s map (check_types_e(get_info(s))) match { - case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors += new InvalidConnect(s.info) + case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors += new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize) case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors += new InvalidRegInit(s.info) - case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors += new InvalidConnect(s.info) + case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors += new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize) case (s:Stop) => { if (wt(tpe(s.clk)) != wt(ClockType()) ) errors += new ReqClk(s.info) if (wt(tpe(s.en)) != wt(ut()) ) errors += new EnNotUInt(s.info) |
