diff options
| author | Donggyu | 2016-09-08 22:02:34 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-08 22:02:33 -0700 |
| commit | 2010bc4fc7ae1b2f263505ab069dcf1b7c0f56af (patch) | |
| tree | 3e849452a97548174cfc42a20c254ff949a7d1fc /src/main | |
| parent | 765b880d4a56875c1ed07f4a0e8904c74a92dc0b (diff) | |
| parent | 5878c08b46b2520760800db73e0ef4b21f173f46 (diff) | |
Merge pull request #288 from ucb-bar/revert-to-keyset-fix
Revert to keyset
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/ExpandWhens.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala index 7c013b51..dcefb20f 100644 --- a/src/main/scala/firrtl/passes/ExpandWhens.scala +++ b/src/main/scala/firrtl/passes/ExpandWhens.scala @@ -114,7 +114,9 @@ object ExpandWhens extends Pass { val conseqStmt = expandWhens(conseqNetlist, netlist +: defaults, AND(p, s.pred))(s.conseq) val altStmt = expandWhens(altNetlist, netlist +: defaults, AND(p, NOT(s.pred)))(s.alt) - val memos = (conseqNetlist.keys ++ altNetlist.keys) map { lvalue => + // Process combined set of keys because we only want to create 1 mux for each node + // being connected to in the conseq and/or alt + val memos = (conseqNetlist.keySet ++ altNetlist.keySet) map { lvalue => // Defaults in netlist get priority over those in defaults val default = netlist get lvalue match { case Some(v) => Some(v) |