diff options
| author | Schuyler Eldridge | 2018-06-13 16:56:44 -0400 |
|---|---|---|
| committer | Jack Koenig | 2018-06-13 13:56:44 -0700 |
| commit | 7bdde21a68362663cc7356ce4b659d012a10b3e4 (patch) | |
| tree | d209edd7277a3d7a88779b7d0a451d094db50869 /src/main | |
| parent | 5d7bbb2e42b19762a6408f3d9c4925a5eba37f76 (diff) | |
Resolve register clock dependencies in RemoveWires (#823)
Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/RemoveWires.scala | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala index 5ba953cd..8cc967dd 100644 --- a/src/main/scala/firrtl/transforms/RemoveWires.scala +++ b/src/main/scala/firrtl/transforms/RemoveWires.scala @@ -40,7 +40,8 @@ class RemoveWires extends Transform { // Transform netlist into DefNodes private def getOrderedNodes( - netlist: mutable.LinkedHashMap[WrappedExpression, (Expression, Info)]): Try[Seq[DefNode]] = { + netlist: mutable.LinkedHashMap[WrappedExpression, (Expression, Info)], + regInfo: mutable.Map[WrappedExpression, DefRegister]): Try[Seq[Statement]] = { val digraph = new MutableDiGraph[WrappedExpression] for ((sink, (expr, _)) <- netlist) { digraph.addVertex(sink) @@ -55,9 +56,12 @@ class RemoveWires extends Transform { Try { val ordered = digraph.linearize.reverse ordered.map { key => - val WRef(name, _,_,_) = key.e1 + val WRef(name, _, kind, _) = key.e1 val (rhs, info) = netlist(key) - DefNode(info, name, rhs) + kind match { + case RegKind => regInfo(key) + case _ => DefNode(info, name, rhs) + } } } } @@ -71,6 +75,8 @@ class RemoveWires extends Transform { val netlist = mutable.LinkedHashMap.empty[WrappedExpression, (Expression, Info)] // Info at definition of wires for combining into node val wireInfo = mutable.HashMap.empty[WrappedExpression, Info] + // Additional info about registers + val regInfo = mutable.HashMap.empty[WrappedExpression, DefRegister] def onStmt(stmt: Statement): Statement = { stmt match { @@ -78,6 +84,9 @@ class RemoveWires extends Transform { netlist(we(WRef(name))) = (expr, info) case wire: DefWire if !wire.tpe.isInstanceOf[AnalogType] => // Remove all non-Analog wires wireInfo(WRef(wire)) = wire.info + case reg: DefRegister => + regInfo(we(WRef(reg))) = reg + netlist(we(WRef(reg))) = (reg.clock, reg.info) case decl: IsDeclaration => // Keep all declarations except for nodes and non-Analog wires decls += decl case con @ Connect(cinfo, lhs, rhs) => kind(lhs) match { @@ -107,7 +116,7 @@ class RemoveWires extends Transform { m match { case mod @ Module(info, name, ports, body) => onStmt(body) - getOrderedNodes(netlist) match { + getOrderedNodes(netlist, regInfo) match { case Success(logic) => Module(info, name, ports, Block(decls ++ logic ++ otherStmts)) // If we hit a CyclicException, just abort removing wires |