diff options
| author | Donggyu | 2016-11-03 23:57:24 -0700 |
|---|---|---|
| committer | GitHub | 2016-11-03 23:57:24 -0700 |
| commit | 62133264a788f46b319ebab9c31424b7e0536101 (patch) | |
| tree | 3e665bf2677de23da9ea51bbe402ec7080f5ac62 /src/main | |
| parent | 097cd70a1f44a4181297e4e6dadaec03f4c92636 (diff) | |
| parent | 324157eececc774401012577a92ae05082a7a12d (diff) | |
Merge pull request #363 from ucb-bar/fix-sint-assign
Add Legalize to MiddleToLowFirrtl
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index f42d11ba..446df6d0 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -127,7 +127,8 @@ class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun { passes.InferTypes, passes.ResolveGenders, passes.InferWidths, - passes.ConvertFixedToSInt) + passes.ConvertFixedToSInt, + passes.Legalize) def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = run(circuit, passSeq) } |