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authorazidar2015-07-30 18:26:40 -0700
committerazidar2015-07-30 18:26:40 -0700
commit2440b824c68e4604d174e92e26af2c3eca1ec171 (patch)
treeda4417c923631571cb4247f351f17bfb7739f13d /src/main/stanza/passes.stanza
parent30d3b50982a40eefeb5a2abcc8d85da1af88d84f (diff)
Added module name to error messages.
Diffstat (limited to 'src/main/stanza/passes.stanza')
-rw-r--r--src/main/stanza/passes.stanza5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index d84b08a5..d5034f8a 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1611,8 +1611,8 @@ public defn expand-whens (c:Circuit) -> Circuit :
;for x in resets do : println-debug(x)
val table = merge-resets(assign,resets,rsignals)
- println("====== Table ======")
- for x in table do : println(x)
+ ;println-debug("====== Table ======")
+ ;for x in table do : println-debug(x)
val decs = Vector<Stmt>()
val cons = Vector<Stmt>()
@@ -1626,7 +1626,6 @@ public defn expand-whens (c:Circuit) -> Circuit :
referenced?[key(x)] = true
for x in decs do :
mark-referenced(referenced?,x)
- println-all(["Referenced \n" referenced?])
val decs* = Vector<Stmt>()
for x in decs do :
if is-referenced?(referenced?,x) : add(decs*,x)