diff options
| author | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
| commit | 70567d4d57ac178660fbef0ef660069b52857562 (patch) | |
| tree | ac0ed0127ddb99a72cbc760f6be97b99c574d018 /src/main/stanza/ir-parser.stanza | |
| parent | 98bb81d9d99150a80c77ed8f22d44748a02df628 (diff) | |
Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!
Had to separate initialization check pass
Need to write dead code elimination pass
Added LongWidth to support dshl that are huge
Diffstat (limited to 'src/main/stanza/ir-parser.stanza')
| -rw-r--r-- | src/main/stanza/ir-parser.stanza | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 96c50c3c..5b7c1106 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -210,7 +210,10 @@ defsyntax firrtl : accdir = (rdwr) : RDWR defrule width : - width = (?x:#int) : IntWidth(x) + width = (?x:#intorlong) : + match(x) : + (x:Int) : IntWidth(x) + (x:Long) : LongWidth(x) width = (?) : UnknownWidth() ;Main Statement Productions |