From 70567d4d57ac178660fbef0ef660069b52857562 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Fri, 17 Jul 2015 16:49:22 -0700
Subject: Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! Had to
 separate initialization check pass Need to write dead code elimination pass
 Added LongWidth to support dshl that are huge

---
 src/main/stanza/ir-parser.stanza | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/main/stanza/ir-parser.stanza')

diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 96c50c3c..5b7c1106 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -210,7 +210,10 @@ defsyntax firrtl :
       accdir = (rdwr) : RDWR
 
    defrule width :
-      width = (?x:#int) : IntWidth(x)
+      width = (?x:#intorlong) : 
+         match(x) : 
+            (x:Int) : IntWidth(x)
+            (x:Long) : LongWidth(x)
       width = (?) : UnknownWidth()
 
    ;Main Statement Productions
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