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authorJack Koenig2019-05-24 14:37:52 -0700
committerGitHub2019-05-24 14:37:52 -0700
commit228c9a4b7432ac52178d63b8f27fe064aec71e9c (patch)
treefd131f6c97fbfb8aab722af34fc1d174bfd93dc4 /src/main/scala/tutorial
parent524b8957e36a7ac931ca0fe042a64fce80195057 (diff)
Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)
Emit Verilog IntParams that fit in 32-bits as Integer literals
Diffstat (limited to 'src/main/scala/tutorial')
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