Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794)

Add optional argument to verilogToCpp to suppress VCD

1 files changed, 13 insertions, 7 deletions

diff --git a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
index 97c9c5e3..0c5ab12f 100644
--- a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
+++ b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
@@ -7,6 +7,8 @@ import java.nio.file.Files
 import java.text.SimpleDateFormat
 import java.util.Calendar
 
+import firrtl.FirrtlExecutionOptions
+
 import scala.sys.process.{ProcessBuilder, ProcessLogger, _}
  
 trait BackendCompilationUtilities {
@@ -83,11 +85,13 @@ trait BackendCompilationUtilities {
     * @param cppHarness C++ testharness to compile/link against
     */
   def verilogToCpp(
-                    dutFile: String,
-                    dir: File,
-                    vSources: Seq[File],
-                    cppHarness: File
-                  ): ProcessBuilder = {
+    dutFile: String,
+    dir: File,
+    vSources: Seq[File],
+    cppHarness: File,
+    suppressVcd: Boolean = false
+  ): ProcessBuilder = {
+
     val topModule = dutFile
 
     val blackBoxVerilogList = {
@@ -109,8 +113,10 @@ trait BackendCompilationUtilities {
       Seq("--assert",
         "-Wno-fatal",
         "-Wno-WIDTH",
-        "-Wno-STMTDLY",
-        "--trace",
+        "-Wno-STMTDLY"
+      ) ++
+      { if(suppressVcd) { Seq.empty } else { Seq("--trace")} } ++
+      Seq(
         "-O1",
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,