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authorChick Markley2017-02-01 20:43:21 -0800
committerGitHub2017-02-01 20:43:21 -0800
commit32af1d4fafc64ddb669b313e627b2e3a308dc1ab (patch)
tree8a9f512a4657337ad233ff90935a94f5c90670ed /src/main/scala/firrtl/util/BackendCompilationUtilities.scala
parenta017bf38f72e1d7dd1bd59e7cd7beb77a50e4259 (diff)
Fix anno in backend (#428)
* fixed up impementation of deleteDirectoryHierarchy Added a few more tests * Round 2 of moving verilog to target dir Only create .f file if some files have been moved Some small style fixes in Driver Restored lost functionality to add -f argument in verilogToCpp Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
Diffstat (limited to 'src/main/scala/firrtl/util/BackendCompilationUtilities.scala')
-rw-r--r--src/main/scala/firrtl/util/BackendCompilationUtilities.scala28
1 files changed, 19 insertions, 9 deletions
diff --git a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
index 8c07192b..8f4ab73d 100644
--- a/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
+++ b/src/main/scala/firrtl/util/BackendCompilationUtilities.scala
@@ -2,16 +2,12 @@
package firrtl.util
-import scala.sys.process._
import java.io._
import java.nio.file.Files
import java.text.SimpleDateFormat
import java.util.Calendar
-import firrtl._
-import firrtl.{Driver, ExecutionOptionsManager}
-
-import scala.sys.process.{ProcessBuilder, ProcessLogger}
+import scala.sys.process.{ProcessBuilder, ProcessLogger, _}
trait BackendCompilationUtilities {
/** Parent directory for tests */
@@ -93,8 +89,22 @@ trait BackendCompilationUtilities {
cppHarness: File
): ProcessBuilder = {
val topModule = dutFile
- val command = Seq("verilator",
- "--cc", s"$dutFile.v") ++
+
+ val blackBoxVerilogList = {
+ val list_file = new File(dir, firrtl.transforms.BlackBoxSourceHelper.FileListName)
+ if(list_file.exists()) {
+ Seq("-f", list_file.getAbsolutePath)
+ }
+ else {
+ Seq.empty[String]
+ }
+ }
+
+ val command = Seq(
+ "verilator",
+ "--cc", s"$dutFile.v"
+ ) ++
+ blackBoxVerilogList ++
vSources.flatMap(file => Seq("-v", file.getAbsolutePath)) ++
Seq("--assert",
"-Wno-fatal",
@@ -115,7 +125,7 @@ trait BackendCompilationUtilities {
}
def cppToExe(prefix: String, dir: File): ProcessBuilder =
- Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}")
+ Seq("make", "-C", dir.toString, "-j", "-f", s"V$prefix.mk", s"V$prefix")
def executeExpectingFailure(
prefix: String,
@@ -123,7 +133,7 @@ trait BackendCompilationUtilities {
assertionMsg: String = ""): Boolean = {
var triggered = false
val assertionMessageSupplied = assertionMsg != ""
- val e = Process(s"./V${prefix}", dir) !
+ val e = Process(s"./V$prefix", dir) !
ProcessLogger(line => {
triggered = triggered || (assertionMessageSupplied && line.contains(assertionMsg))
System.out.println(line) // scalastyle:ignore regex