All of src/ formatted with scalafmt

1 files changed, 15 insertions, 12 deletions

diff --git a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
index 840a3d99..ae3bc693 100644
--- a/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
+++ b/src/main/scala/firrtl/transforms/RemoveKeywordCollisions.scala
@@ -21,10 +21,11 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends ManipulateNames {
     * @return Some name if a rename occurred, None otherwise
     * @note prefix uniqueness is not respected
     */
-  override def manipulate = (n: String, ns: Namespace) => keywords.contains(n) match {
-    case true  => Some(Uniquify.findValidPrefix(n + inlineDelim, Seq(""), ns.cloneUnderlying ++ keywords))
-    case false => None
-  }
+  override def manipulate = (n: String, ns: Namespace) =>
+    keywords.contains(n) match {
+      case true  => Some(Uniquify.findValidPrefix(n + inlineDelim, Seq(""), ns.cloneUnderlying ++ keywords))
+      case false => None
+    }
 
 }
 
@@ -32,14 +33,16 @@ class RemoveKeywordCollisions(keywords: Set[String]) extends ManipulateNames {
 class VerilogRename extends RemoveKeywordCollisions(v_keywords) {
 
   override def prerequisites = firrtl.stage.Forms.LowFormMinimumOptimized ++
-    Seq( Dependency[BlackBoxSourceHelper],
-         Dependency[FixAddingNegativeLiterals],
-         Dependency[ReplaceTruncatingArithmetic],
-         Dependency[InlineBitExtractionsTransform],
-         Dependency[InlineCastsTransform],
-         Dependency[LegalizeClocksTransform],
-         Dependency[FlattenRegUpdate],
-         Dependency(passes.VerilogModulusCleanup) )
+    Seq(
+      Dependency[BlackBoxSourceHelper],
+      Dependency[FixAddingNegativeLiterals],
+      Dependency[ReplaceTruncatingArithmetic],
+      Dependency[InlineBitExtractionsTransform],
+      Dependency[InlineCastsTransform],
+      Dependency[LegalizeClocksTransform],
+      Dependency[FlattenRegUpdate],
+      Dependency(passes.VerilogModulusCleanup)
+    )
 
   override def optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized