diff options
| author | Schuyler Eldridge | 2019-12-17 18:29:47 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-03-11 14:01:31 -0400 |
| commit | abf226471249a1cbb8de33d0c4bc8526f9aafa70 (patch) | |
| tree | 0537dff3091db3da167c0fffc3388a5966c46204 /src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala | |
| parent | 646c91e71b8bfb1b0d0f22e81ca113147637ce71 (diff) | |
Migrate to DependencyAPI
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala')
| -rw-r--r-- | src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala index 08bf4af4..59d14ab2 100644 --- a/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala +++ b/src/main/scala/firrtl/transforms/FixAddingNegativeLiteralsTransform.scala @@ -2,10 +2,12 @@ package firrtl.transforms -import firrtl.{CircuitState, LowForm, Namespace, PrimOps, Transform, Utils, WRef} +import firrtl.{CircuitState, Namespace, PrimOps, Transform, UnknownForm, Utils, WRef} import firrtl.ir._ import firrtl.Mappers._ +import firrtl.options.{Dependency, PreservesAll} import firrtl.PrimOps.{Add, AsSInt, Sub, Tail} +import firrtl.stage.Forms import scala.collection.mutable @@ -105,9 +107,15 @@ object FixAddingNegativeLiterals { * the literal and thus not all expressions in the add are the same. This is fixed here when we directly * subtract the literal instead. */ -class FixAddingNegativeLiterals extends Transform { - def inputForm = LowForm - def outputForm = LowForm +class FixAddingNegativeLiterals extends Transform with PreservesAll[Transform] { + def inputForm = UnknownForm + def outputForm = UnknownForm + + override val prerequisites = Forms.LowFormMinimumOptimized :+ Dependency[BlackBoxSourceHelper] + + override val optionalPrerequisites = firrtl.stage.Forms.LowFormOptimized + + override val dependents = Seq.empty def execute(state: CircuitState): CircuitState = { val modulesx = state.circuit.modules.map(FixAddingNegativeLiterals.fixupModule) |
